| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[0].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[1].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[2].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[3].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[4].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[5].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[6].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 1985 | 1 | T3 | 3 | T7 | 1 | T19 | 1 | ||||
| auto[2] | 27810 | 1 | T3 | 9 | T7 | 4 | T19 | 4 | ||||
| auto[3] | 27764 | 1 | T3 | 9 | T7 | 4 | T19 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 195 | 1 | T23 | 1 | T13 | 1 | T14 | 1 | ||||
| auto[2] | 5427 | 1 | T23 | 4 | T13 | 4 | T14 | 62 | ||||
| auto[3] | 5419 | 1 | T23 | 4 | T13 | 4 | T14 | 62 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 175 | 1 | T12 | 1 | T13 | 1 | T18 | 2 | ||||
| auto[2] | 4788 | 1 | T12 | 16 | T13 | 102 | T18 | 5 | ||||
| auto[3] | 4776 | 1 | T12 | 16 | T13 | 102 | T18 | 5 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 173 | 1 | T1 | 1 | T14 | 1 | T11 | 2 | ||||
| auto[2] | 5424 | 1 | T1 | 4 | T14 | 5 | T11 | 5 | ||||
| auto[3] | 5420 | 1 | T1 | 4 | T14 | 5 | T11 | 5 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 141 | 1 | T13 | 1 | T14 | 1 | T24 | 1 | ||||
| auto[2] | 3547 | 1 | T13 | 28 | T14 | 5 | T24 | 16 | ||||
| auto[3] | 3537 | 1 | T13 | 28 | T14 | 5 | T24 | 16 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 131 | 1 | T13 | 1 | T14 | 1 | T25 | 1 | ||||
| auto[2] | 3438 | 1 | T13 | 62 | T14 | 74 | T25 | 61 | ||||
| auto[3] | 3430 | 1 | T13 | 62 | T14 | 74 | T25 | 61 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 116 | 1 | T14 | 1 | T26 | 1 | T27 | 1 | ||||
| auto[2] | 3556 | 1 | T14 | 4 | T26 | 4 | T27 | 4 | ||||
| auto[3] | 3554 | 1 | T14 | 4 | T26 | 4 | T27 | 4 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |