Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	673027	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5412299

1

T1

54

T2

11

T3

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1609491	1			T1	13		T2	1		T3	28
values[0x0]	2070262	1			T1	26		T2	14		T3	25
values[0x1]	2405573	1			T1	34		T2	13		T3	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	334007	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5751319

1

T1

62

T2

16

T3

56

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23530	1			T14	2		T64	6		T71	2
valid_sources[0x01]	22896	1			T20	89		T48	1		T21	289
valid_sources[0x02]	24569	1			T12	1		T25	2		T71	1
valid_sources[0x03]	25860	1			T12	3		T18	2		T57	2
valid_sources[0x04]	25673	1			T12	1		T16	4		T17	2
valid_sources[0x05]	22960	1			T25	2		T20	141		T48	1
valid_sources[0x06]	22734	1			T25	4		T20	116		T48	1
valid_sources[0x07]	24639	1			T3	1		T10	3		T284	3
valid_sources[0x08]	25589	1			T19	1		T11	69		T57	2
valid_sources[0x09]	23648	1			T16	2		T35	1		T25	1
valid_sources[0x0a]	23551	1			T19	2		T57	1		T25	3
valid_sources[0x0b]	22117	1			T13	1		T17	1		T25	6
valid_sources[0x0c]	24714	1			T17	1		T25	1		T20	121
valid_sources[0x0d]	24069	1			T35	1		T284	4		T20	136
valid_sources[0x0e]	24276	1			T3	2		T19	1		T13	1
valid_sources[0x0f]	22072	1			T12	2		T25	4		T20	116
valid_sources[0x10]	21912	1			T12	1		T17	1		T25	5
valid_sources[0x11]	23289	1			T19	1		T13	2		T14	1
valid_sources[0x12]	23124	1			T25	4		T63	2		T64	1
valid_sources[0x13]	24646	1			T13	1		T25	1		T27	1
valid_sources[0x14]	23827	1			T10	2		T25	5		T71	4
valid_sources[0x15]	23639	1			T23	1		T25	1		T20	66
valid_sources[0x16]	24174	1			T3	1		T13	1		T14	1
valid_sources[0x17]	24170	1			T19	2		T13	1		T14	2
valid_sources[0x18]	23900	1			T12	1		T45	1		T20	93
valid_sources[0x19]	23903	1			T13	1		T17	1		T25	1
valid_sources[0x1a]	22629	1			T12	1		T14	1		T17	2
valid_sources[0x1b]	26188	1			T12	1		T57	1		T17	1
valid_sources[0x1c]	24960	1			T13	1		T14	1		T25	1
valid_sources[0x1d]	24168	1			T27	1		T20	111		T21	325
valid_sources[0x1e]	22162	1			T19	1		T18	1		T57	1
valid_sources[0x1f]	23961	1			T14	2		T17	1		T25	3
valid_sources[0x20]	23507	1			T12	2		T64	2		T20	123
valid_sources[0x21]	24456	1			T12	3		T13	1		T25	1
valid_sources[0x22]	25071	1			T14	1		T57	1		T25	4
valid_sources[0x23]	25979	1			T35	1		T17	2		T20	134
valid_sources[0x24]	24613	1			T14	3		T17	1		T25	1
valid_sources[0x25]	25142	1			T12	1		T16	3		T25	6
valid_sources[0x26]	23690	1			T25	2		T20	94		T21	231
valid_sources[0x27]	23842	1			T19	2		T13	1		T25	5
valid_sources[0x28]	23765	1			T18	2		T4	3		T25	1
valid_sources[0x29]	25174	1			T19	1		T13	1		T25	1
valid_sources[0x2a]	23023	1			T7	2		T5	2		T63	1
valid_sources[0x2b]	23193	1			T7	1		T18	1		T57	1
valid_sources[0x2c]	23914	1			T12	3		T71	1		T27	2
valid_sources[0x2d]	23194	1			T3	44		T13	1		T14	2
valid_sources[0x2e]	25701	1			T2	1		T3	3		T13	1
valid_sources[0x2f]	23845	1			T10	4		T16	3		T17	1
valid_sources[0x30]	24017	1			T3	1		T5	4		T17	1
valid_sources[0x31]	23793	1			T14	5		T18	1		T276	1
valid_sources[0x32]	23686	1			T19	2		T5	9		T25	2
valid_sources[0x33]	22587	1			T13	1		T18	1		T35	1
valid_sources[0x34]	23297	1			T2	1		T13	1		T57	1
valid_sources[0x35]	23666	1			T14	1		T10	1		T18	2
valid_sources[0x36]	24194	1			T17	1		T284	9		T20	116
valid_sources[0x37]	22255	1			T57	2		T27	1		T20	94
valid_sources[0x38]	23336	1			T18	1		T17	1		T64	3
valid_sources[0x39]	23405	1			T2	1		T3	1		T14	2
valid_sources[0x3a]	23982	1			T275	1		T276	4		T20	97
valid_sources[0x3b]	23606	1			T10	1		T25	2		T45	8
valid_sources[0x3c]	22925	1			T13	1		T18	1		T5	1
valid_sources[0x3d]	23079	1			T13	1		T14	1		T16	1
valid_sources[0x3e]	24479	1			T25	1		T20	92		T47	1
valid_sources[0x3f]	22998	1			T7	1		T25	4		T20	117
valid_sources[0x40]	23432	1			T7	3		T13	1		T14	1
valid_sources[0x41]	22539	1			T2	1		T13	1		T16	2
valid_sources[0x42]	22740	1			T57	1		T25	1		T64	2
valid_sources[0x43]	24664	1			T3	3		T13	1		T14	1
valid_sources[0x44]	24276	1			T57	2		T71	3		T27	1
valid_sources[0x45]	26349	1			T19	3		T35	1		T27	1
valid_sources[0x46]	25324	1			T5	1		T25	1		T20	106
valid_sources[0x47]	22718	1			T12	2		T35	1		T25	2
valid_sources[0x48]	22218	1			T7	4		T13	1		T14	5
valid_sources[0x49]	23973	1			T13	1		T18	1		T35	1
valid_sources[0x4a]	24092	1			T13	1		T14	2		T20	121
valid_sources[0x4b]	26454	1			T16	22		T17	1		T25	1
valid_sources[0x4c]	23103	1			T13	1		T5	1		T17	1
valid_sources[0x4d]	23556	1			T19	1		T13	1		T25	1
valid_sources[0x4e]	23148	1			T18	1		T16	1		T71	2
valid_sources[0x4f]	22590	1			T19	1		T12	1		T14	1
valid_sources[0x50]	24139	1			T13	1		T14	1		T25	1
valid_sources[0x51]	22099	1			T13	2		T10	1		T18	2
valid_sources[0x52]	24742	1			T12	1		T17	1		T72	2
valid_sources[0x53]	22921	1			T19	1		T12	2		T25	3
valid_sources[0x54]	24681	1			T19	2		T10	1		T57	1
valid_sources[0x55]	22529	1			T3	1		T27	1		T276	4
valid_sources[0x56]	25272	1			T12	4		T14	1		T25	9
valid_sources[0x57]	24462	1			T14	2		T17	1		T63	1
valid_sources[0x58]	23299	1			T2	1		T25	3		T64	1
valid_sources[0x59]	22366	1			T14	2		T57	1		T25	1
valid_sources[0x5a]	26635	1			T12	1		T18	1		T64	1
valid_sources[0x5b]	24261	1			T14	2		T35	1		T17	1
valid_sources[0x5c]	24777	1			T12	4		T13	1		T10	2
valid_sources[0x5d]	23589	1			T19	1		T12	1		T17	1
valid_sources[0x5e]	22806	1			T19	1		T13	1		T10	3
valid_sources[0x5f]	21933	1			T18	1		T57	1		T17	1
valid_sources[0x60]	23768	1			T12	1		T16	1		T17	1
valid_sources[0x61]	24087	1			T2	2		T19	1		T13	1
valid_sources[0x62]	22724	1			T13	1		T14	1		T10	2
valid_sources[0x63]	23299	1			T12	1		T14	2		T25	2
valid_sources[0x64]	23687	1			T25	4		T63	1		T27	3
valid_sources[0x65]	23395	1			T13	1		T14	1		T10	3
valid_sources[0x66]	23593	1			T12	2		T25	1		T64	3
valid_sources[0x67]	25184	1			T13	2		T64	1		T72	1
valid_sources[0x68]	24151	1			T2	1		T12	1		T25	2
valid_sources[0x69]	25808	1			T19	1		T5	2		T25	7
valid_sources[0x6a]	23436	1			T3	1		T12	1		T18	1
valid_sources[0x6b]	23341	1			T13	1		T16	6		T20	67
valid_sources[0x6c]	24916	1			T19	1		T12	3		T35	1
valid_sources[0x6d]	23961	1			T3	2		T10	2		T17	1
valid_sources[0x6e]	23552	1			T19	1		T57	2		T25	10
valid_sources[0x6f]	24164	1			T19	1		T27	1		T20	149
valid_sources[0x70]	23416	1			T19	1		T13	2		T14	5
valid_sources[0x71]	24627	1			T19	1		T13	1		T25	2
valid_sources[0x72]	24945	1			T2	1		T35	1		T25	1
valid_sources[0x73]	24575	1			T3	1		T64	2		T20	96
valid_sources[0x74]	23105	1			T14	2		T57	6		T25	6
valid_sources[0x75]	23504	1			T19	1		T35	2		T17	2
valid_sources[0x76]	24656	1			T57	1		T62	1		T63	1
valid_sources[0x77]	23973	1			T14	3		T35	1		T17	1
valid_sources[0x78]	22467	1			T12	2		T57	1		T20	134
valid_sources[0x79]	23922	1			T2	1		T13	3		T5	1
valid_sources[0x7a]	23807	1			T19	1		T12	2		T13	1
valid_sources[0x7b]	23052	1			T3	1		T12	2		T13	1
valid_sources[0x7c]	23051	1			T2	2		T14	2		T17	2
valid_sources[0x7d]	23268	1			T13	2		T17	1		T63	2
valid_sources[0x7e]	23575	1			T13	2		T10	2		T18	2
valid_sources[0x7f]	24861	1			T25	4		T72	1		T20	91
valid_sources[0x80]	24983	1			T25	2		T72	1		T20	138

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1361965

1

T1

2

T3

10

T7

3

values[0x0]

all_enables

biggest_size

2027001

1

T1

25

T2

5

T3

21

values[0x1]

all_enables

biggest_size

2023333

1

T1

27

T2

6

T3

18