Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2643	1			T1	4		T12	3		T13	2
non_zero_bins[1]	1898	1			T12	5		T13	6		T14	38
zero	9376	1			T3	5		T7	3		T19	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	498	1			T284	1		T20	7		T21	9
uni	3693	1			T7	1		T19	1		T12	1
gen	4425	1			T3	3		T7	1		T19	1
res	864	1			T1	3		T12	2		T13	2
ins	4437	1			T1	1		T3	2		T7	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9389

1

T1

4

T3

2

T7

3

mubi_true

4528

1

T3

3

T12

3

T13

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

23

1

T65

1

T285

1

T74

1

pass

13894

1

T1

4

T3

5

T7

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	111	1			T20	4		T21	4		T36	1
upd	non_zero_bins[0]	pass	mubi_true	126	1			T284	1		T20	2		T21	4
upd	non_zero_bins[1]	pass	mubi_false	81	1			T21	1		T248	1		T22	1
upd	non_zero_bins[1]	pass	mubi_true	78	1			T22	2		T224	3		T225	1
upd	zero	pass	mubi_false	50	1			T20	1		T36	1		T22	2
upd	zero	pass	mubi_true	52	1			T98	1		T225	1		T226	1
uni	zero	pass	mubi_false	2754	1			T7	1		T19	1		T12	1
uni	zero	pass	mubi_true	939	1			T25	1		T96	5		T27	1
gen	non_zero_bins[0]	pass	mubi_false	538	1			T12	1		T14	1		T28	1
gen	non_zero_bins[0]	pass	mubi_true	473	1			T10	8		T16	3		T24	4
gen	non_zero_bins[1]	pass	mubi_false	413	1			T12	5		T13	6		T14	37
gen	non_zero_bins[1]	pass	mubi_true	304	1			T31	1		T20	2		T46	3
gen	zero	fail	mubi_false	18	1			T65	1		T285	1		T74	1
gen	zero	pass	mubi_false	1968	1			T3	1		T7	1		T19	1
gen	zero	pass	mubi_true	711	1			T3	2		T18	2		T11	2
res	non_zero_bins[0]	pass	mubi_false	221	1			T1	3		T17	2		T96	1
res	non_zero_bins[0]	pass	mubi_true	197	1			T12	2		T13	2		T16	4
res	non_zero_bins[1]	pass	mubi_false	121	1			T46	2		T36	2		T22	2
res	non_zero_bins[1]	pass	mubi_true	141	1			T10	2		T20	1		T21	2
res	zero	fail	mubi_false	5	1			T286	1		T287	1		T288	1
res	zero	pass	mubi_false	103	1			T14	2		T64	1		T277	2
res	zero	pass	mubi_true	76	1			T21	1		T36	1		T289	1
ins	non_zero_bins[0]	pass	mubi_false	508	1			T1	1		T28	1		T17	1
ins	non_zero_bins[0]	pass	mubi_true	469	1			T25	2		T96	2		T276	1
ins	non_zero_bins[1]	pass	mubi_false	380	1			T14	1		T10	1		T96	1
ins	non_zero_bins[1]	pass	mubi_true	380	1			T28	1		T16	1		T27	2
ins	zero	pass	mubi_false	2118	1			T3	1		T7	1		T19	1
ins	zero	pass	mubi_true	582	1			T3	1		T12	1		T13	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded