SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 24 | 1 | T64 | 2 | T74 | 2 | T192 | 2 | ||||
others[1] | 19 | 1 | T73 | 2 | T68 | 2 | T167 | 2 | ||||
others[2] | 19 | 1 | T219 | 2 | T306 | 2 | T78 | 1 | ||||
others[3] | 34 | 1 | T62 | 2 | T307 | 2 | T79 | 1 | ||||
false | 3562 | 1 | T1 | 2 | T3 | 11 | T7 | 1 | ||||
true | 825 | 1 | T1 | 5 | T3 | 2 | T12 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 21 | 1 | T285 | 2 | T215 | 2 | T302 | 2 | ||||
others[1] | 33 | 1 | T57 | 2 | T47 | 2 | T104 | 2 | ||||
others[2] | 24 | 1 | T18 | 2 | T239 | 2 | T204 | 2 | ||||
others[3] | 36 | 1 | T11 | 2 | T35 | 2 | T185 | 2 | ||||
false | 3779 | 1 | T1 | 7 | T3 | 12 | T7 | 1 | ||||
true | 590 | 1 | T3 | 1 | T23 | 2 | T18 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 14 | 1 | T308 | 1 | T218 | 1 | T309 | 1 | ||||
others[1] | 17 | 1 | T63 | 1 | T97 | 1 | T178 | 1 | ||||
others[2] | 16 | 1 | T69 | 1 | T301 | 1 | T310 | 1 | ||||
others[3] | 20 | 1 | T311 | 1 | T187 | 1 | T312 | 1 | ||||
false | 3566 | 1 | T1 | 5 | T3 | 10 | T7 | 1 | ||||
true | 850 | 1 | T1 | 2 | T3 | 3 | T12 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 24 | 1 | T65 | 2 | T313 | 2 | T188 | 2 | ||||
others[1] | 28 | 1 | T72 | 2 | T160 | 2 | T166 | 2 | ||||
others[2] | 21 | 1 | T3 | 2 | T100 | 2 | T250 | 2 | ||||
others[3] | 28 | 1 | T71 | 2 | T105 | 2 | T303 | 2 | ||||
false | 1997 | 1 | T1 | 5 | T3 | 7 | T12 | 2 | ||||
true | 2385 | 1 | T1 | 2 | T3 | 4 | T7 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |