Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T23,T26,T50
1	1	Covered	T3,T23,T18

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T19
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T12,T13

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T18,T11
1	0	Covered	T4,T5,T6

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T3,T18,T11
1	Covered	T4,T5,T6

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T3,T18,T11
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T18,T11
1	Covered	T4,T5,T6

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T23

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T12,T13
AutoCaptGenCnt	143	Covered	T1,T12,T13
AutoCaptReseedCnt	141	Covered	T1,T12,T13
AutoDispatch	125	Covered	T1,T12,T13
AutoFirstAckWait	119	Covered	T1,T12,T13
AutoLoadIns	69	Covered	T1,T12,T13
AutoSendGenCmd	150	Covered	T1,T12,T13
AutoSendReseedCmd	162	Covered	T1,T12,T13
BootDone	98	Covered	T3,T23,T28
BootGenAckWait	90	Covered	T3,T23,T28
BootInsAckWait	80	Covered	T3,T23,T18
BootLoadGen	85	Covered	T3,T23,T18
BootLoadIns	65	Covered	T3,T23,T18
BootLoadUni	102	Covered	T28,T35,T31
BootPulse	94	Covered	T3,T23,T28
BootUniAckWait	107	Covered	T28,T35,T31
Error	188	Covered	T4,T5,T6
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T3,T18,T11
SWPortMode	74	Covered	T3,T7,T19

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T12,T13
AutoAckWait->Error	188	Covered	T39,T126,T144
AutoAckWait->Idle	211	Covered	T1,T16,T56
AutoAckWait->RejectCsrngEntropy	188	Covered	T57,T64,T72
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T12,T13
AutoCaptGenCnt->Error	188	Covered	T5,T145,T146
AutoCaptGenCnt->Idle	211	Covered	T115,T132,T147
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T11,T148,T149
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T1,T12,T13
AutoCaptReseedCnt->Error	188	Covered	T150,T151,T152
AutoCaptReseedCnt->Idle	211	Covered	T153,T154,T155
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T156,T157,T158
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T12,T13
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T12,T13
AutoDispatch->Error	188	Covered	T159
AutoDispatch->Idle	138	Covered	T12,T13,T14
AutoDispatch->RejectCsrngEntropy	188	Covered	T160,T161,T162
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T12,T13
AutoFirstAckWait->Error	188	Covered	T163,T164,T141
AutoFirstAckWait->Idle	211	Covered	T1,T56,T165
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T166,T167,T104
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T12,T13
AutoLoadIns->Error	188	Covered	T8,T9,T40
AutoLoadIns->Idle	211	Covered	T57,T5,T63
AutoLoadIns->RejectCsrngEntropy	188	Covered	T62,T71,T100
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T12,T13
AutoSendGenCmd->Error	188	Covered	T101,T140,T168
AutoSendGenCmd->Idle	211	Covered	T91,T124,T169
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T170,T102,T171
AutoSendReseedCmd->AutoAckWait	168	Covered	T1,T12,T13
AutoSendReseedCmd->Error	188	Covered	T172,T173,T174
AutoSendReseedCmd->Idle	211	Covered	T175,T176,T177
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T178,T179,T180
BootDone->BootLoadUni	102	Covered	T28,T35,T31
BootDone->Error	188	Covered	T181
BootDone->Idle	211	Covered	T26,T182,T183
BootDone->RejectCsrngEntropy	188	Covered	T3,T63,T73
BootGenAckWait->BootPulse	94	Covered	T3,T23,T28
BootGenAckWait->Error	188	Covered	T123
BootGenAckWait->Idle	211	Covered	T51,T184,T113
BootGenAckWait->RejectCsrngEntropy	188	Covered	T105,T74,T185
BootInsAckWait->BootLoadGen	85	Covered	T3,T23,T18
BootInsAckWait->Error	188	Covered	T58,T43,T186
BootInsAckWait->Idle	211	Covered	T23,T58,T59
BootInsAckWait->RejectCsrngEntropy	188	Covered	T187,T188,T189
BootLoadGen->BootGenAckWait	90	Covered	T3,T23,T28
BootLoadGen->Error	188	Covered	T59,T134,T190
BootLoadGen->Idle	211	Covered	T108,T138,T191
BootLoadGen->RejectCsrngEntropy	188	Covered	T18,T192,T193
BootLoadIns->BootInsAckWait	80	Covered	T3,T23,T18
BootLoadIns->Error	188	Covered	T194,T195,T196
BootLoadIns->Idle	211	Covered	T197,T198,T199
BootLoadIns->RejectCsrngEntropy	188	Covered	T200,T201,T202
BootLoadUni->BootUniAckWait	107	Covered	T28,T35,T31
BootLoadUni->Error	188	Covered	T203
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T204,T205,T206
BootPulse->BootDone	98	Covered	T3,T23,T28
BootPulse->Error	188	Not Covered
BootPulse->Idle	211	Covered	T50,T106,T207
BootPulse->RejectCsrngEntropy	188	Covered	T208,T209,T210
BootUniAckWait->Error	188	Covered	T184,T44,T211
BootUniAckWait->Idle	112	Covered	T28,T31,T69
BootUniAckWait->RejectCsrngEntropy	188	Covered	T35,T47,T97
Idle->AutoLoadIns	69	Covered	T1,T12,T13
Idle->BootLoadIns	65	Covered	T3,T23,T18
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T3,T62,T71
Idle->SWPortMode	74	Covered	T3,T7,T19
RejectCsrngEntropy->Error	188	Covered	T6,T15,T212
RejectCsrngEntropy->Idle	211	Covered	T3,T18,T11
SWPortMode->Error	188	Covered	T60,T38,T41
SWPortMode->Idle	211	Covered	T3,T18,T11
SWPortMode->RejectCsrngEntropy	188	Covered	T18,T11,T57

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T18
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T13
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T19
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T18
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T18
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T18
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T18
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T28
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T28
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T28
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T35,T31
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T3,T23,T26
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T35,T31
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T28,T35,T31
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T28,T35,T31
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T12,T13
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T12,T13
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T12,T13
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T12,T13
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T12,T13
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T12,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T12,T13,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T12,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T12,T13
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T12,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T12,T13,T14
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T12,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T12,T13
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T19
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T11
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T51,T94

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T5,T6
1	0	1	-	Not Covered
1	0	0	-	Covered	T3,T18,T11
0	-	-	1	Covered	T1,T3,T23
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	209386385	83339	0	0
FpvSecCmErrorStEscalate_A	209386385	83468	0	0
u_state_regs_A	209354801	209248620	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	83339	0	0
T4	663	300	0	0
T5	1093	285	0	0
T6	653	320	0	0
T8	0	192	0	0
T15	0	399	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	370	0	0
T52	920	0	0	0
T58	0	664	0	0
T59	0	1000	0	0
T60	0	290	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	220	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	83468	0	0
T4	663	301	0	0
T5	1093	286	0	0
T6	653	321	0	0
T8	0	193	0	0
T15	0	400	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	371	0	0
T52	920	0	0	0
T58	0	665	0	0
T59	0	1001	0	0
T60	0	291	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	221	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209354801	209248620	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0