Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T23

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T7,T19
DataWait	75	Covered	T3,T7,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T50,T106,T107
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T7,T19
DataWait->AckPls	80	Covered	T3,T7,T19
DataWait->Disabled	107	Covered	T23,T108,T109
DataWait->Error	99	Covered	T5,T8,T58
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T110,T111,T112
EndPointClear->Error	99	Covered	T9,T113,T114
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T3,T7,T19
Idle->Disabled	107	Covered	T1,T3,T23
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T3,T7,T19
Idle	-	1	0	-	Covered	T3,T7,T19
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T3,T7,T19
DataWait	-	-	-	0	Covered	T3,T7,T19
AckPls	-	-	-	-	Covered	T3,T7,T19
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T5,T6,T58

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1465704695	594773	0	0
FpvSecCmErrorStEscalate_A	1465704695	595676	0	0
u_state_regs_A	1465673111	1464929844	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1465704695	594773	0	0
T4	4641	2450	0	0
T5	7651	1945	0	0
T6	4571	2190	0	0
T8	0	1344	0	0
T15	0	2793	0	0
T17	24220	0	0	0
T25	14952	0	0	0
T26	7329	0	0	0
T51	0	2940	0	0
T52	6440	0	0	0
T58	0	4598	0	0
T59	0	6950	0	0
T60	0	1980	0	0
T62	15148	0	0	0
T63	19544	0	0	0
T64	16457	0	0	0
T94	0	1890	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1465704695	595676	0	0
T4	4641	2457	0	0
T5	7651	1952	0	0
T6	4571	2197	0	0
T8	0	1351	0	0
T15	0	2800	0	0
T17	24220	0	0	0
T25	14952	0	0	0
T26	7329	0	0	0
T51	0	2947	0	0
T52	6440	0	0	0
T58	0	4605	0	0
T59	0	6957	0	0
T60	0	1987	0	0
T62	15148	0	0	0
T63	19544	0	0	0
T64	16457	0	0	0
T94	0	1897	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1465673111	1464929844	0	0
T1	18676	18018	0	0
T2	10451	10024	0	0
T3	12887	12495	0	0
T7	12446	11781	0	0
T10	14077	13440	0	0
T12	14847	14483	0	0
T13	29477	29036	0	0
T14	34475	33810	0	0
T19	12894	12306	0	0
T23	8029	7630	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T13,T14
DataWait	75	Covered	T23,T13,T14
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T13,T14
DataWait->AckPls	80	Covered	T23,T13,T14
DataWait->Disabled	107	Covered	T23,T115,T116
DataWait->Error	99	Covered	T117,T118,T119
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T110,T111,T112
EndPointClear->Error	99	Covered	T9,T113,T114
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T23,T13,T14
Idle->Disabled	107	Covered	T1,T3,T18
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T23,T13,T14
Idle	-	1	0	-	Covered	T23,T13,T14
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T23,T13,T14
DataWait	-	-	-	0	Covered	T23,T13,T14
AckPls	-	-	-	-	Covered	T23,T13,T14
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209386385	85339	0	0
FpvSecCmErrorStEscalate_A	209386385	85468	0	0
u_state_regs_A	209386385	209280204	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85339	0	0
T4	663	350	0	0
T5	1093	285	0	0
T6	653	320	0	0
T8	0	192	0	0
T15	0	399	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	420	0	0
T52	920	0	0	0
T58	0	664	0	0
T59	0	1000	0	0
T60	0	290	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85468	0	0
T4	663	351	0	0
T5	1093	286	0	0
T6	653	321	0	0
T8	0	193	0	0
T15	0	400	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	421	0	0
T52	920	0	0	0
T58	0	665	0	0
T59	0	1001	0	0
T60	0	291	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T12,T13,T18
DataWait	75	Covered	T12,T13,T18
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T12,T13,T18
DataWait->AckPls	80	Covered	T12,T13,T18
DataWait->Disabled	107	Covered	T120,T121,T122
DataWait->Error	99	Covered	T5,T58,T123
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T110,T111,T112
EndPointClear->Error	99	Covered	T9,T113,T114
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T12,T13,T18
Idle->Disabled	107	Covered	T1,T3,T23
Idle->Error	99	Covered	T4,T6,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T12,T13,T18
Idle	-	1	0	-	Covered	T12,T13,T18
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T12,T13,T18
DataWait	-	-	-	0	Covered	T12,T13,T18
AckPls	-	-	-	-	Covered	T12,T13,T18
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209386385	85339	0	0
FpvSecCmErrorStEscalate_A	209386385	85468	0	0
u_state_regs_A	209386385	209280204	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85339	0	0
T4	663	350	0	0
T5	1093	285	0	0
T6	653	320	0	0
T8	0	192	0	0
T15	0	399	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	420	0	0
T52	920	0	0	0
T58	0	664	0	0
T59	0	1000	0	0
T60	0	290	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85468	0	0
T4	663	351	0	0
T5	1093	286	0	0
T6	653	321	0	0
T8	0	193	0	0
T15	0	400	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	421	0	0
T52	920	0	0	0
T58	0	665	0	0
T59	0	1001	0	0
T60	0	291	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T13,T14,T24
DataWait	75	Covered	T13,T14,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T13,T14,T24
DataWait->AckPls	80	Covered	T13,T14,T24
DataWait->Disabled	107	Covered	T109,T124,T125
DataWait->Error	99	Covered	T15,T126,T127
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T110,T111,T112
EndPointClear->Error	99	Covered	T9,T113,T114
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T13,T14,T24
Idle->Disabled	107	Covered	T1,T3,T23
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T13,T14,T24
Idle	-	1	0	-	Covered	T13,T14,T24
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T13,T14,T24
DataWait	-	-	-	0	Covered	T13,T14,T24
AckPls	-	-	-	-	Covered	T13,T14,T24
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209386385	85339	0	0
FpvSecCmErrorStEscalate_A	209386385	85468	0	0
u_state_regs_A	209386385	209280204	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85339	0	0
T4	663	350	0	0
T5	1093	285	0	0
T6	653	320	0	0
T8	0	192	0	0
T15	0	399	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	420	0	0
T52	920	0	0	0
T58	0	664	0	0
T59	0	1000	0	0
T60	0	290	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85468	0	0
T4	663	351	0	0
T5	1093	286	0	0
T6	653	321	0	0
T8	0	193	0	0
T15	0	400	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	421	0	0
T52	920	0	0	0
T58	0	665	0	0
T59	0	1001	0	0
T60	0	291	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T14,T26,T27
DataWait	75	Covered	T14,T26,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T14,T26,T27
DataWait->AckPls	80	Covered	T14,T26,T27
DataWait->Disabled	107	Covered	T128,T129,T130
DataWait->Error	99	Covered	T131
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T110,T111,T112
EndPointClear->Error	99	Covered	T9,T113,T114
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T14,T26,T27
Idle->Disabled	107	Covered	T1,T3,T23
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T14,T26,T27
Idle	-	1	0	-	Covered	T14,T26,T27
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T14,T26,T27
DataWait	-	-	-	0	Covered	T14,T26,T27
AckPls	-	-	-	-	Covered	T14,T26,T27
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209386385	85339	0	0
FpvSecCmErrorStEscalate_A	209386385	85468	0	0
u_state_regs_A	209386385	209280204	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85339	0	0
T4	663	350	0	0
T5	1093	285	0	0
T6	653	320	0	0
T8	0	192	0	0
T15	0	399	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	420	0	0
T52	920	0	0	0
T58	0	664	0	0
T59	0	1000	0	0
T60	0	290	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85468	0	0
T4	663	351	0	0
T5	1093	286	0	0
T6	653	321	0	0
T8	0	193	0	0
T15	0	400	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	421	0	0
T52	920	0	0	0
T58	0	665	0	0
T59	0	1001	0	0
T60	0	291	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T14,T11
DataWait	75	Covered	T1,T14,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T106,T107
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T14,T11
DataWait->AckPls	80	Covered	T1,T14,T11
DataWait->Disabled	107	Covered	T132,T133
DataWait->Error	99	Covered	T134,T135,T136
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T110,T111,T112
EndPointClear->Error	99	Covered	T9,T113,T114
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T1,T14,T11
Idle->Disabled	107	Covered	T1,T3,T23
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T1,T14,T11
Idle	-	1	0	-	Covered	T1,T14,T11
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T1,T14,T11
DataWait	-	-	-	0	Covered	T1,T14,T11
AckPls	-	-	-	-	Covered	T1,T14,T11
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209386385	85339	0	0
FpvSecCmErrorStEscalate_A	209386385	85468	0	0
u_state_regs_A	209386385	209280204	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85339	0	0
T4	663	350	0	0
T5	1093	285	0	0
T6	653	320	0	0
T8	0	192	0	0
T15	0	399	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	420	0	0
T52	920	0	0	0
T58	0	664	0	0
T59	0	1000	0	0
T60	0	290	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85468	0	0
T4	663	351	0	0
T5	1093	286	0	0
T6	653	321	0	0
T8	0	193	0	0
T15	0	400	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	421	0	0
T52	920	0	0	0
T58	0	665	0	0
T59	0	1001	0	0
T60	0	291	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T13,T14,T25
DataWait	75	Covered	T13,T14,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T137
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T13,T14,T25
DataWait->AckPls	80	Covered	T13,T14,T25
DataWait->Disabled	107	Covered	T138,T139
DataWait->Error	99	Covered	T140,T141
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T110,T111,T112
EndPointClear->Error	99	Covered	T9,T113,T114
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T13,T14,T25
Idle->Disabled	107	Covered	T1,T3,T23
Idle->Error	99	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T13,T14,T25
Idle	-	1	0	-	Covered	T13,T14,T25
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T13,T14,T25
DataWait	-	-	-	0	Covered	T13,T14,T25
AckPls	-	-	-	-	Covered	T13,T14,T25
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209386385	85339	0	0
FpvSecCmErrorStEscalate_A	209386385	85468	0	0
u_state_regs_A	209386385	209280204	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85339	0	0
T4	663	350	0	0
T5	1093	285	0	0
T6	653	320	0	0
T8	0	192	0	0
T15	0	399	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	420	0	0
T52	920	0	0	0
T58	0	664	0	0
T59	0	1000	0	0
T60	0	290	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85468	0	0
T4	663	351	0	0
T5	1093	286	0	0
T6	653	321	0	0
T8	0	193	0	0
T15	0	400	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	421	0	0
T52	920	0	0	0
T58	0	665	0	0
T59	0	1001	0	0
T60	0	291	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T7,T19
DataWait	75	Covered	T3,T7,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T4,T5,T6
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T50
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T7,T19
DataWait->AckPls	80	Covered	T3,T7,T19
DataWait->Disabled	107	Covered	T108,T91,T142
DataWait->Error	99	Covered	T8,T143,T39
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T110,T111,T112
EndPointClear->Error	99	Covered	T9,T113,T114
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T3,T7,T19
Idle->Disabled	107	Covered	T1,T3,T23
Idle->Error	99	Covered	T4,T51,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T3,T7,T19
Idle	-	1	0	-	Covered	T3,T7,T19
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T3,T7,T19
DataWait	-	-	-	0	Covered	T3,T7,T19
AckPls	-	-	-	-	Covered	T3,T7,T19
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T5,T6,T58

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T3,T23
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209386385	82739	0	0
FpvSecCmErrorStEscalate_A	209386385	82868	0	0
u_state_regs_A	209354801	209248620	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	82739	0	0
T4	663	350	0	0
T5	1093	235	0	0
T6	653	270	0	0
T8	0	192	0	0
T15	0	399	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	420	0	0
T52	920	0	0	0
T58	0	614	0	0
T59	0	950	0	0
T60	0	240	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	82868	0	0
T4	663	351	0	0
T5	1093	236	0	0
T6	653	271	0	0
T8	0	193	0	0
T15	0	400	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T51	0	421	0	0
T52	920	0	0	0
T58	0	615	0	0
T59	0	951	0	0
T60	0	241	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209354801	209248620	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0