Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.13	100.00	90.29			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T84,T88,T89
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T85,T86,T87
1	0	1	Covered	T1,T3,T12
1	1	0	Not Covered
1	1	1	Covered	T1,T12,T13

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	418432116	636403	0	0
DepthKnown_A	418772770	418560408	0	0
RvalidKnown_A	418772770	418560408	0	0
WreadyKnown_A	418772770	418560408	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	418772770	718673	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418432116	636403	0	0
T1	5336	2690	0	0
T2	2986	0	0	0
T3	3682	69	0	0
T7	3556	0	0	0
T10	4022	1759	0	0
T11	0	378	0	0
T12	4242	1110	0	0
T13	8422	2451	0	0
T14	9850	6409	0	0
T16	0	2499	0	0
T19	3684	0	0	0
T23	2294	0	0	0
T24	0	541	0	0
T57	0	881	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418772770	418560408	0	0
T1	5336	5148	0	0
T2	2986	2864	0	0
T3	3682	3570	0	0
T7	3556	3366	0	0
T10	4022	3840	0	0
T12	4242	4138	0	0
T13	8422	8296	0	0
T14	9850	9660	0	0
T19	3684	3516	0	0
T23	2294	2180	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418772770	418560408	0	0
T1	5336	5148	0	0
T2	2986	2864	0	0
T3	3682	3570	0	0
T7	3556	3366	0	0
T10	4022	3840	0	0
T12	4242	4138	0	0
T13	8422	8296	0	0
T14	9850	9660	0	0
T19	3684	3516	0	0
T23	2294	2180	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418772770	418560408	0	0
T1	5336	5148	0	0
T2	2986	2864	0	0
T3	3682	3570	0	0
T7	3556	3366	0	0
T10	4022	3840	0	0
T12	4242	4138	0	0
T13	8422	8296	0	0
T14	9850	9660	0	0
T19	3684	3516	0	0
T23	2294	2180	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	418772770	718673	0	0
T1	5336	2690	0	0
T2	2986	0	0	0
T3	3682	69	0	0
T7	3556	0	0	0
T10	4022	1759	0	0
T11	0	378	0	0
T12	4242	1110	0	0
T13	8422	2451	0	0
T14	9850	6409	0	0
T16	0	2499	0	0
T19	3684	0	0	0
T23	2294	0	0	0
T24	0	541	0	0
T57	0	881	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T72,T90,T91
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T88,T89
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T85,T87
1	0	1	Covered	T1,T3,T12
1	1	0	Not Covered
1	1	1	Covered	T1,T12,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	209216058	311820	0	0
DepthKnown_A	209386385	209280204	0	0
RvalidKnown_A	209386385	209280204	0	0
WreadyKnown_A	209386385	209280204	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	209386385	352847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209216058	311820	0	0
T1	2668	1311	0	0
T2	1493	0	0	0
T3	1841	33	0	0
T7	1778	0	0	0
T10	2011	875	0	0
T11	0	190	0	0
T12	2121	517	0	0
T13	4211	1194	0	0
T14	4925	3139	0	0
T16	0	1171	0	0
T19	1842	0	0	0
T23	1147	0	0	0
T24	0	261	0	0
T57	0	383	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	352847	0	0
T1	2668	1311	0	0
T2	1493	0	0	0
T3	1841	33	0	0
T7	1778	0	0	0
T10	2011	875	0	0
T11	0	190	0	0
T12	2121	517	0	0
T13	4211	1194	0	0
T14	4925	3139	0	0
T16	0	1171	0	0
T19	1842	0	0	0
T23	1147	0	0	0
T24	0	261	0	0
T57	0	383	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T84
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T86,T92,T93
1	0	1	Covered	T1,T3,T12
1	1	0	Not Covered
1	1	1	Covered	T1,T12,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	209216058	324583	0	0
DepthKnown_A	209386385	209280204	0	0
RvalidKnown_A	209386385	209280204	0	0
WreadyKnown_A	209386385	209280204	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	209386385	365826	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209216058	324583	0	0
T1	2668	1379	0	0
T2	1493	0	0	0
T3	1841	36	0	0
T7	1778	0	0	0
T10	2011	884	0	0
T11	0	188	0	0
T12	2121	593	0	0
T13	4211	1257	0	0
T14	4925	3270	0	0
T16	0	1328	0	0
T19	1842	0	0	0
T23	1147	0	0	0
T24	0	280	0	0
T57	0	498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	365826	0	0
T1	2668	1379	0	0
T2	1493	0	0	0
T3	1841	36	0	0
T7	1778	0	0	0
T10	2011	884	0	0
T11	0	188	0	0
T12	2121	593	0	0
T13	4211	1257	0	0
T14	4925	3270	0	0
T16	0	1328	0	0
T19	1842	0	0	0
T23	1147	0	0	0
T24	0	280	0	0
T57	0	498	0	0