Group : tb.dut.u_edn_cov_if::edn_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cfg_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cfg_cg 100.00 1 100 1 64 64




Group Instance : edn_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 21 0 21 100.00


Variables for Group Instance edn_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 0 3 100.00 100 1 1 0
cp_num_boot_reqs 2 0 2 100.00 100 1 1 0
cp_num_endpoints 7 0 7 100.00 100 1 1 8


Crosses for Group Instance edn_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_num_endpoints_mode 21 0 21 100.00 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
both 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
boot_req_mode 133 1 T2 1 T25 1 T26 1
auto_req_mode 132 1 T9 1 T17 1 T18 1
sw_mode 2923 1 T1 10 T3 1 T4 4



Summary for Variable cp_num_boot_reqs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 298 1 T2 1 T9 1 T25 1
single 102 1 T27 1 T57 1 T34 1



Summary for Variable cp_num_endpoints

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1299 1 T2 1 T3 1 T21 1
auto[2] 125 1 T76 1 T35 1 T133 28
auto[3] 203 1 T27 1 T134 87 T303 1
auto[4] 181 1 T37 1 T23 40 T64 1
auto[5] 41 1 T304 1 T305 1 T306 1
auto[6] 97 1 T26 1 T13 1 T73 1
auto[7] 1242 1 T1 10 T9 1 T4 4



Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 21 0 21 100.00


Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins
cp_num_endpointscp_modeCOUNTSTATUS
[auto[0]] [boot_req_mode , auto_req_mode , sw_mode] -- Excluded (3 bins)


Covered bins
cp_num_endpointscp_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] boot_req_mode 88 1 T2 1 T25 1 T34 1
auto[1] auto_req_mode 77 1 T18 1 T12 1 T38 1
auto[1] sw_mode 1134 1 T3 1 T21 1 T57 1
auto[2] boot_req_mode 2 1 T307 1 T308 1 - -
auto[2] auto_req_mode 6 1 T35 1 T63 1 T309 1
auto[2] sw_mode 117 1 T76 1 T133 28 T310 8
auto[3] boot_req_mode 4 1 T311 1 T312 1 T313 1
auto[3] auto_req_mode 1 1 T314 1 - - - -
auto[3] sw_mode 198 1 T27 1 T134 87 T303 1
auto[4] boot_req_mode 2 1 T37 1 T66 1 - -
auto[4] auto_req_mode 3 1 T315 1 T316 1 T317 1
auto[4] sw_mode 176 1 T23 40 T64 1 T67 1
auto[5] boot_req_mode 4 1 T305 1 T306 1 T318 1
auto[5] auto_req_mode 5 1 T319 1 T320 1 T321 1
auto[5] sw_mode 32 1 T304 1 T322 1 T323 1
auto[6] boot_req_mode 3 1 T26 1 T324 1 T325 1
auto[6] auto_req_mode 7 1 T13 1 T73 1 T326 1
auto[6] sw_mode 87 1 T327 1 T328 1 T329 25
auto[7] boot_req_mode 30 1 T28 1 T39 1 T33 1
auto[7] auto_req_mode 33 1 T9 1 T17 1 T41 1
auto[7] sw_mode 1179 1 T1 10 T4 4 T44 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%