Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	690968	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5568169

1

T1

236

T2

40

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1650086	1			T1	681		T2	83		T3	20
values[0x0]	2128603	1			T1	113		T2	24		T3	3
values[0x1]	2480448	1			T1	114		T2	18		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	340602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5918535

1

T1

439

T2

65

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23991	1			T1	7		T28	1		T75	2
valid_sources[0x01]	22934	1			T1	4		T75	1		T8	4
valid_sources[0x02]	23669	1			T1	2		T27	1		T28	1
valid_sources[0x03]	24179	1			T1	3		T2	3		T4	3
valid_sources[0x04]	25182	1			T1	3		T28	1		T75	1
valid_sources[0x05]	24581	1			T1	5		T3	27		T18	5
valid_sources[0x06]	23613	1			T1	5		T27	1		T19	1
valid_sources[0x07]	24314	1			T1	3		T4	5		T20	1
valid_sources[0x08]	23741	1			T1	3		T2	3		T4	20
valid_sources[0x09]	25249	1			T2	2		T27	1		T11	2
valid_sources[0x0a]	24940	1			T1	10		T75	3		T30	1
valid_sources[0x0b]	24137	1			T1	1		T25	1		T28	2
valid_sources[0x0c]	25554	1			T1	5		T28	2		T75	3
valid_sources[0x0d]	24742	1			T1	7		T57	2		T7	1
valid_sources[0x0e]	23733	1			T1	1		T2	6		T28	2
valid_sources[0x0f]	25103	1			T1	3		T28	2		T75	1
valid_sources[0x10]	24566	1			T1	3		T2	3		T55	1
valid_sources[0x11]	25097	1			T1	3		T27	1		T30	1
valid_sources[0x12]	24304	1			T1	1		T27	1		T20	1
valid_sources[0x13]	23407	1			T1	7		T27	4		T20	1
valid_sources[0x14]	24597	1			T1	3		T28	2		T12	2
valid_sources[0x15]	22880	1			T1	1		T28	3		T29	1
valid_sources[0x16]	22983	1			T1	5		T27	4		T55	1
valid_sources[0x17]	23976	1			T1	3		T5	1		T27	1
valid_sources[0x18]	24823	1			T1	4		T10	2		T20	1
valid_sources[0x19]	23780	1			T1	5		T2	1		T29	1
valid_sources[0x1a]	24639	1			T1	3		T27	1		T28	2
valid_sources[0x1b]	24883	1			T1	1		T4	1		T11	3
valid_sources[0x1c]	24243	1			T57	3		T19	2		T28	2
valid_sources[0x1d]	24625	1			T1	5		T28	1		T75	2
valid_sources[0x1e]	24074	1			T1	6		T27	1		T28	1
valid_sources[0x1f]	25121	1			T1	3		T10	3		T28	2
valid_sources[0x20]	24616	1			T1	1		T10	4		T27	1
valid_sources[0x21]	23827	1			T1	4		T28	1		T75	1
valid_sources[0x22]	24873	1			T1	3		T4	2		T27	1
valid_sources[0x23]	24356	1			T1	4		T4	8		T5	1
valid_sources[0x24]	24519	1			T1	1		T5	1		T27	2
valid_sources[0x25]	23831	1			T1	1		T27	1		T28	2
valid_sources[0x26]	21910	1			T1	5		T4	15		T20	1
valid_sources[0x27]	23970	1			T1	4		T27	2		T28	1
valid_sources[0x28]	24644	1			T1	4		T2	5		T28	2
valid_sources[0x29]	24175	1			T1	6		T4	10		T27	1
valid_sources[0x2a]	24089	1			T1	3		T10	70		T27	3
valid_sources[0x2b]	23029	1			T1	1		T27	1		T28	1
valid_sources[0x2c]	24642	1			T1	1		T27	1		T57	1
valid_sources[0x2d]	24776	1			T1	4		T2	3		T20	1
valid_sources[0x2e]	23260	1			T1	5		T2	2		T28	2
valid_sources[0x2f]	23047	1			T1	5		T20	1		T19	1
valid_sources[0x30]	25372	1			T1	4		T57	2		T76	1
valid_sources[0x31]	23466	1			T1	6		T4	1		T28	3
valid_sources[0x32]	23136	1			T1	3		T29	2		T75	4
valid_sources[0x33]	24669	1			T1	4		T19	1		T28	1
valid_sources[0x34]	24309	1			T1	5		T28	1		T30	1
valid_sources[0x35]	25668	1			T1	4		T28	1		T75	1
valid_sources[0x36]	23896	1			T1	2		T4	1		T27	1
valid_sources[0x37]	25220	1			T1	6		T28	2		T29	1
valid_sources[0x38]	25082	1			T1	4		T11	1		T76	2
valid_sources[0x39]	24789	1			T1	5		T28	3		T75	2
valid_sources[0x3a]	23814	1			T1	3		T30	2		T22	162
valid_sources[0x3b]	23944	1			T1	1		T4	9		T27	1
valid_sources[0x3c]	24487	1			T1	3		T28	3		T75	1
valid_sources[0x3d]	25777	1			T1	6		T76	2		T54	1
valid_sources[0x3e]	23866	1			T1	1		T27	2		T29	2
valid_sources[0x3f]	24735	1			T1	1		T27	2		T20	2
valid_sources[0x40]	23921	1			T1	3		T28	1		T29	1
valid_sources[0x41]	23992	1			T4	21		T27	1		T75	1
valid_sources[0x42]	22795	1			T1	5		T2	1		T4	3
valid_sources[0x43]	24188	1			T1	5		T27	1		T57	4
valid_sources[0x44]	24441	1			T1	5		T75	1		T76	1
valid_sources[0x45]	24790	1			T1	3		T27	1		T75	1
valid_sources[0x46]	26776	1			T1	3		T11	1		T28	2
valid_sources[0x47]	23267	1			T1	5		T2	4		T11	1
valid_sources[0x48]	24620	1			T1	7		T4	5		T28	4
valid_sources[0x49]	24083	1			T1	5		T4	17		T5	2
valid_sources[0x4a]	24266	1			T1	5		T4	4		T20	1
valid_sources[0x4b]	24283	1			T1	2		T27	1		T57	3
valid_sources[0x4c]	24635	1			T1	4		T27	1		T20	1
valid_sources[0x4d]	25035	1			T1	2		T28	1		T22	130
valid_sources[0x4e]	24250	1			T1	6		T27	1		T75	1
valid_sources[0x4f]	23559	1			T20	1		T57	7		T19	1
valid_sources[0x50]	25435	1			T1	5		T27	1		T7	3
valid_sources[0x51]	25150	1			T1	2		T28	2		T7	5
valid_sources[0x52]	25259	1			T1	3		T75	2		T30	2
valid_sources[0x53]	23671	1			T1	6		T4	4		T29	1
valid_sources[0x54]	24859	1			T1	3		T2	4		T4	4
valid_sources[0x55]	24341	1			T1	2		T75	2		T22	120
valid_sources[0x56]	25907	1			T1	4		T75	1		T76	1
valid_sources[0x57]	23878	1			T1	4		T10	1		T27	1
valid_sources[0x58]	25362	1			T1	4		T2	2		T11	2
valid_sources[0x59]	24220	1			T1	7		T27	2		T11	1
valid_sources[0x5a]	22588	1			T1	1		T5	1		T20	1
valid_sources[0x5b]	24823	1			T1	4		T57	3		T55	1
valid_sources[0x5c]	23341	1			T1	1		T28	2		T75	1
valid_sources[0x5d]	23886	1			T1	6		T4	2		T11	1
valid_sources[0x5e]	24084	1			T4	6		T28	2		T75	2
valid_sources[0x5f]	26069	1			T1	6		T27	1		T19	1
valid_sources[0x60]	27108	1			T1	7		T4	5		T27	1
valid_sources[0x61]	23367	1			T1	4		T19	1		T28	1
valid_sources[0x62]	23959	1			T1	2		T2	1		T27	1
valid_sources[0x63]	25672	1			T1	5		T4	1		T20	1
valid_sources[0x64]	24583	1			T1	3		T75	1		T53	1
valid_sources[0x65]	25543	1			T1	4		T4	2		T5	1
valid_sources[0x66]	25461	1			T1	3		T28	1		T76	2
valid_sources[0x67]	25095	1			T1	3		T75	3		T8	2
valid_sources[0x68]	25201	1			T1	4		T28	1		T29	2
valid_sources[0x69]	24363	1			T1	3		T2	1		T28	1
valid_sources[0x6a]	24398	1			T1	2		T4	2		T28	1
valid_sources[0x6b]	24379	1			T1	8		T4	2		T28	2
valid_sources[0x6c]	23290	1			T1	4		T2	2		T4	1
valid_sources[0x6d]	24286	1			T1	3		T2	5		T4	2
valid_sources[0x6e]	24893	1			T1	2		T27	3		T57	2
valid_sources[0x6f]	24306	1			T1	4		T55	1		T75	2
valid_sources[0x70]	25556	1			T5	2		T75	3		T30	2
valid_sources[0x71]	24428	1			T1	2		T28	1		T75	1
valid_sources[0x72]	24039	1			T1	2		T2	2		T29	1
valid_sources[0x73]	25589	1			T1	4		T4	12		T27	2
valid_sources[0x74]	24815	1			T1	7		T4	11		T27	1
valid_sources[0x75]	25023	1			T1	8		T4	5		T5	1
valid_sources[0x76]	24130	1			T1	5		T28	2		T75	1
valid_sources[0x77]	22877	1			T1	5		T37	134		T75	1
valid_sources[0x78]	25576	1			T1	1		T30	1		T22	152
valid_sources[0x79]	22833	1			T1	5		T5	2		T27	1
valid_sources[0x7a]	26237	1			T1	2		T27	1		T28	3
valid_sources[0x7b]	25127	1			T1	6		T5	1		T28	2
valid_sources[0x7c]	26356	1			T1	5		T4	5		T27	1
valid_sources[0x7d]	24471	1			T1	4		T8	2		T30	3
valid_sources[0x7e]	24521	1			T1	4		T28	2		T75	2
valid_sources[0x7f]	24391	1			T1	1		T27	1		T28	2
valid_sources[0x80]	24723	1			T1	6		T2	4		T55	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1401842

1

T1

68

T2

4

T3

2

values[0x0]

all_enables

biggest_size

2083957

1

T1

86

T2

20

T3

1

values[0x1]

all_enables

biggest_size

2082370

1

T1

82

T2

16

T3

4