Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2625	1			T1	7		T9	4		T4	1
non_zero_bins[1]	1858	1			T1	6		T2	3		T9	2
zero	9496	1			T1	23		T2	4		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	534	1			T1	3		T27	1		T26	1
uni	3719	1			T1	11		T2	2		T3	1
gen	4399	1			T1	10		T2	2		T3	1
res	856	1			T1	1		T2	1		T9	2
ins	4471	1			T1	11		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9141

1

T1

29

T2

2

T3

2

mubi_true

4838

1

T1

7

T2

5

T3

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

23

1

T10

1

T11

1

T54

1

pass

13956

1

T1

36

T2

7

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	111	1			T22	2		T23	1		T24	2
upd	non_zero_bins[0]	pass	mubi_true	139	1			T1	1		T27	1		T30	1
upd	non_zero_bins[1]	pass	mubi_false	88	1			T57	1		T22	2		T24	1
upd	non_zero_bins[1]	pass	mubi_true	85	1			T1	1		T23	1		T24	1
upd	zero	pass	mubi_false	50	1			T1	1		T26	1		T22	1
upd	zero	pass	mubi_true	61	1			T23	2		T24	3		T225	1
uni	zero	pass	mubi_false	2719	1			T1	10		T2	2		T9	1
uni	zero	pass	mubi_true	1000	1			T1	1		T3	1		T4	2
gen	non_zero_bins[0]	pass	mubi_false	460	1			T1	2		T9	3		T17	11
gen	non_zero_bins[0]	pass	mubi_true	473	1			T1	2		T17	1		T75	1
gen	non_zero_bins[1]	pass	mubi_false	333	1			T1	1		T4	1		T27	1
gen	non_zero_bins[1]	pass	mubi_true	379	1			T2	1		T58	1		T37	1
gen	zero	fail	mubi_false	17	1			T11	1		T54	1		T279	1
gen	zero	pass	mubi_false	1958	1			T1	5		T3	1		T9	1
gen	zero	pass	mubi_true	779	1			T2	1		T10	2		T25	2
res	non_zero_bins[0]	pass	mubi_false	180	1			T75	1		T12	2		T22	1
res	non_zero_bins[0]	pass	mubi_true	200	1			T37	1		T23	2		T24	2
res	non_zero_bins[1]	pass	mubi_false	131	1			T1	1		T4	1		T17	2
res	non_zero_bins[1]	pass	mubi_true	126	1			T2	1		T9	2		T18	1
res	zero	fail	mubi_false	6	1			T10	1		T185	1		T280	1
res	zero	pass	mubi_false	106	1			T22	1		T36	1		T281	1
res	zero	pass	mubi_true	107	1			T52	1		T22	1		T13	2
ins	non_zero_bins[0]	pass	mubi_false	527	1			T1	1		T28	1		T58	1
ins	non_zero_bins[0]	pass	mubi_true	535	1			T1	1		T9	1		T4	1
ins	non_zero_bins[1]	pass	mubi_false	358	1			T1	3		T27	1		T58	1
ins	non_zero_bins[1]	pass	mubi_true	358	1			T2	1		T26	1		T28	1
ins	zero	pass	mubi_false	2097	1			T1	5		T3	1		T4	3
ins	zero	pass	mubi_true	596	1			T1	1		T2	1		T10	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded