Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T34,T59
1	1	Covered	T2,T25,T26

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T19,T6
1	1	Covered	T9,T10,T11

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T19
1	0	Covered	T6,T7,T8

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T10,T11,T19
1	Covered	T6,T7,T8

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T10,T11,T19
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T10,T11,T19
1	Covered	T6,T7,T8

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T10,T20

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T9,T10,T11
AutoCaptGenCnt	143	Covered	T9,T10,T11
AutoCaptReseedCnt	141	Covered	T9,T10,T17
AutoDispatch	125	Covered	T9,T10,T11
AutoFirstAckWait	119	Covered	T9,T10,T11
AutoLoadIns	69	Covered	T9,T10,T11
AutoSendGenCmd	150	Covered	T9,T10,T11
AutoSendReseedCmd	162	Covered	T9,T10,T17
BootDone	98	Covered	T2,T25,T26
BootGenAckWait	90	Covered	T2,T25,T26
BootInsAckWait	80	Covered	T2,T25,T26
BootLoadGen	85	Covered	T2,T25,T26
BootLoadIns	65	Covered	T2,T25,T26
BootLoadUni	102	Covered	T2,T26,T28
BootPulse	94	Covered	T2,T25,T26
BootUniAckWait	107	Covered	T2,T26,T28
Error	188	Covered	T6,T7,T8
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T10,T11,T19
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T9,T10,T17
AutoAckWait->Error	188	Covered	T124,T152,T153
AutoAckWait->Idle	211	Covered	T18,T38,T154
AutoAckWait->RejectCsrngEntropy	188	Covered	T11,T54,T36
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T9,T10,T11
AutoCaptGenCnt->Error	188	Covered	T117,T115
AutoCaptGenCnt->Idle	211	Covered	T99,T155
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T156,T157,T158
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T9,T10,T17
AutoCaptReseedCnt->Error	188	Covered	T159,T160,T161
AutoCaptReseedCnt->Idle	211	Covered	T18,T162,T163
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T19,T164,T165
AutoDispatch->AutoCaptGenCnt	143	Covered	T9,T10,T11
AutoDispatch->AutoCaptReseedCnt	141	Covered	T9,T10,T17
AutoDispatch->Error	188	Covered	T166,T121
AutoDispatch->Idle	138	Covered	T9,T17,T12
AutoDispatch->RejectCsrngEntropy	188	Covered	T167,T168,T169
AutoFirstAckWait->AutoDispatch	125	Covered	T9,T10,T11
AutoFirstAckWait->Error	188	Covered	T8,T170,T171
AutoFirstAckWait->Idle	211	Covered	T154,T40,T172
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T173,T174,T175
AutoLoadIns->AutoFirstAckWait	119	Covered	T9,T10,T11
AutoLoadIns->Error	188	Covered	T6,T16,T101
AutoLoadIns->Idle	211	Covered	T6,T7,T8
AutoLoadIns->RejectCsrngEntropy	188	Covered	T176,T177,T178
AutoSendGenCmd->AutoAckWait	156	Covered	T9,T10,T11
AutoSendGenCmd->Error	188	Not Covered
AutoSendGenCmd->Idle	211	Covered	T127,T113,T179
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T29,T139,T180
AutoSendReseedCmd->AutoAckWait	168	Covered	T9,T17,T18
AutoSendReseedCmd->Error	188	Covered	T143,T181
AutoSendReseedCmd->Idle	211	Covered	T182,T183,T184
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T10,T144,T185
BootDone->BootLoadUni	102	Covered	T2,T26,T28
BootDone->Error	188	Covered	T186,T187,T188
BootDone->Idle	211	Covered	T25,T34,T32
BootDone->RejectCsrngEntropy	188	Covered	T142,T69,T189
BootGenAckWait->BootPulse	94	Covered	T2,T25,T26
BootGenAckWait->Error	188	Covered	T190
BootGenAckWait->Idle	211	Covered	T191,T112,T109
BootGenAckWait->RejectCsrngEntropy	188	Covered	T146,T192,T149
BootInsAckWait->BootLoadGen	85	Covered	T2,T25,T26
BootInsAckWait->Error	188	Covered	T193,T194,T195
BootInsAckWait->Idle	211	Covered	T59,T61,T103
BootInsAckWait->RejectCsrngEntropy	188	Covered	T140,T148,T141
BootLoadGen->BootGenAckWait	90	Covered	T2,T25,T26
BootLoadGen->Error	188	Covered	T196,T108
BootLoadGen->Idle	211	Covered	T77,T100,T104
BootLoadGen->RejectCsrngEntropy	188	Covered	T197,T198,T199
BootLoadIns->BootInsAckWait	80	Covered	T2,T25,T26
BootLoadIns->Error	188	Covered	T61,T46,T48
BootLoadIns->Idle	211	Covered	T200,T201,T202
BootLoadIns->RejectCsrngEntropy	188	Covered	T203,T204,T205
BootLoadUni->BootUniAckWait	107	Covered	T2,T26,T28
BootLoadUni->Error	188	Covered	T51,T206
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T207,T78,T208
BootPulse->BootDone	98	Covered	T2,T25,T26
BootPulse->Error	188	Covered	T59,T209,T210
BootPulse->Idle	211	Covered	T96,T97,T98
BootPulse->RejectCsrngEntropy	188	Covered	T211,T212,T213
BootUniAckWait->Error	188	Covered	T214,T215
BootUniAckWait->Idle	112	Covered	T2,T26,T28
BootUniAckWait->RejectCsrngEntropy	188	Covered	T138,T147,T216
Idle->AutoLoadIns	69	Covered	T9,T10,T11
Idle->BootLoadIns	65	Covered	T2,T25,T26
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T11,T19,T29
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T42,T125,T217
RejectCsrngEntropy->Idle	211	Covered	T10,T11,T19
SWPortMode->Error	188	Covered	T15,T102,T45
SWPortMode->Idle	211	Covered	T1,T4,T5
SWPortMode->RejectCsrngEntropy	188	Covered	T10,T42,T54

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T26
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T26
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T26
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T26
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T26
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T26
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T26
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T26
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T26,T28
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T25,T29,T34
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T26,T28
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T26,T28
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T26,T28
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T10,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T9,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T9,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T9,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T9,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T9,T17,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T9,T10,T17
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T9,T10,T11
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T9,T11,T17
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T17
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T17,T18
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T10,T17
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T19
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T31,T103

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T6,T7,T8
1	0	1	-	Not Covered
1	0	0	-	Covered	T10,T11,T19
0	-	-	1	Covered	T5,T10,T20
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	221011153	86919	0	0
FpvSecCmErrorStEscalate_A	221011153	87052	0	0
u_state_regs_A	220976217	220873880	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	86919	0	0
T6	1255	281	0	0
T7	1104	292	0	0
T8	1095	522	0	0
T15	0	936	0	0
T29	2303	0	0	0
T31	974	337	0	0
T34	1097	0	0	0
T37	3693	0	0	0
T42	0	253	0	0
T58	1346	0	0	0
T59	0	366	0	0
T61	0	180	0	0
T75	9921	0	0	0
T76	1942	0	0	0
T102	0	348	0	0
T103	0	130	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	87052	0	0
T6	1255	282	0	0
T7	1104	293	0	0
T8	1095	523	0	0
T15	0	937	0	0
T29	2303	0	0	0
T31	974	338	0	0
T34	1097	0	0	0
T37	3693	0	0	0
T42	0	254	0	0
T58	1346	0	0	0
T59	0	367	0	0
T61	0	181	0	0
T75	9921	0	0	0
T76	1942	0	0	0
T102	0	349	0	0
T103	0	131	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220976217	220873880	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	1959	1808	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	669	524	0	0
T21	1039	946	0	0
T27	5763	5691	0	0