Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T60,T91,T93
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T20,T89,T92
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441667042	577894	0	0
DepthKnown_A	442022306	441817632	0	0
RvalidKnown_A	442022306	441817632	0	0
WreadyKnown_A	442022306	441817632	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	442022306	665285	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441667042	577894	0	0
T4	23820	0	0	0
T5	826	0	0	0
T6	0	362	0	0
T7	0	227	0	0
T8	0	85	0	0
T9	7568	5620	0	0
T10	3228	377	0	0
T11	5666	704	0	0
T17	0	2134	0	0
T18	0	4622	0	0
T19	0	1044	0	0
T20	656	0	0	0
T21	2078	0	0	0
T25	1780	0	0	0
T27	11526	0	0	0
T29	0	369	0	0
T43	2658	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442022306	441817632	0	0
T1	34696	34020	0	0
T2	4442	4302	0	0
T3	2174	2068	0	0
T4	23820	22344	0	0
T5	4012	3710	0	0
T9	7568	7388	0	0
T10	3228	3124	0	0
T20	1454	1164	0	0
T21	2078	1892	0	0
T27	11526	11382	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442022306	441817632	0	0
T1	34696	34020	0	0
T2	4442	4302	0	0
T3	2174	2068	0	0
T4	23820	22344	0	0
T5	4012	3710	0	0
T9	7568	7388	0	0
T10	3228	3124	0	0
T20	1454	1164	0	0
T21	2078	1892	0	0
T27	11526	11382	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442022306	441817632	0	0
T1	34696	34020	0	0
T2	4442	4302	0	0
T3	2174	2068	0	0
T4	23820	22344	0	0
T5	4012	3710	0	0
T9	7568	7388	0	0
T10	3228	3124	0	0
T20	1454	1164	0	0
T21	2078	1892	0	0
T27	11526	11382	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	442022306	665285	0	0
T4	23820	0	0	0
T5	4012	0	0	0
T6	0	1308	0	0
T7	0	1020	0	0
T8	0	876	0	0
T9	7568	5620	0	0
T10	3228	377	0	0
T11	5666	704	0	0
T17	0	2134	0	0
T19	0	1044	0	0
T20	1454	0	0	0
T21	2078	0	0	0
T25	1780	0	0	0
T27	11526	0	0	0
T29	0	369	0	0
T42	0	389	0	0
T43	2658	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T60,T35
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T60,T91,T93
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T92,T94
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220833521	282521	0	0
DepthKnown_A	221011153	220908816	0	0
RvalidKnown_A	221011153	220908816	0	0
WreadyKnown_A	221011153	220908816	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	221011153	326032	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220833521	282521	0	0
T4	11910	0	0	0
T5	413	0	0	0
T6	0	168	0	0
T7	0	93	0	0
T8	0	31	0	0
T9	3784	2812	0	0
T10	1614	111	0	0
T11	2833	356	0	0
T17	0	1063	0	0
T18	0	2255	0	0
T19	0	519	0	0
T20	328	0	0	0
T21	1039	0	0	0
T25	890	0	0	0
T27	5763	0	0	0
T29	0	276	0	0
T43	1329	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	326032	0	0
T4	11910	0	0	0
T5	2006	0	0	0
T6	0	603	0	0
T7	0	453	0	0
T8	0	425	0	0
T9	3784	2812	0	0
T10	1614	111	0	0
T11	2833	356	0	0
T17	0	1063	0	0
T19	0	519	0	0
T20	727	0	0	0
T21	1039	0	0	0
T25	890	0	0	0
T27	5763	0	0	0
T29	0	276	0	0
T42	0	201	0	0
T43	1329	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T95
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T20,T89
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220833521	295373	0	0
DepthKnown_A	221011153	220908816	0	0
RvalidKnown_A	221011153	220908816	0	0
WreadyKnown_A	221011153	220908816	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	221011153	339253	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220833521	295373	0	0
T4	11910	0	0	0
T5	413	0	0	0
T6	0	194	0	0
T7	0	134	0	0
T8	0	54	0	0
T9	3784	2808	0	0
T10	1614	266	0	0
T11	2833	348	0	0
T17	0	1071	0	0
T18	0	2367	0	0
T19	0	525	0	0
T20	328	0	0	0
T21	1039	0	0	0
T25	890	0	0	0
T27	5763	0	0	0
T29	0	93	0	0
T43	1329	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	220908816	0	0
T1	17348	17010	0	0
T2	2221	2151	0	0
T3	1087	1034	0	0
T4	11910	11172	0	0
T5	2006	1855	0	0
T9	3784	3694	0	0
T10	1614	1562	0	0
T20	727	582	0	0
T21	1039	946	0	0
T27	5763	5691	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	221011153	339253	0	0
T4	11910	0	0	0
T5	2006	0	0	0
T6	0	705	0	0
T7	0	567	0	0
T8	0	451	0	0
T9	3784	2808	0	0
T10	1614	266	0	0
T11	2833	348	0	0
T17	0	1071	0	0
T19	0	525	0	0
T20	727	0	0	0
T21	1039	0	0	0
T25	890	0	0	0
T27	5763	0	0	0
T29	0	93	0	0
T42	0	188	0	0
T43	1329	0	0	0