Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	712280	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5816693

1

T1

8

T2

48

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1714424	1			T1	4		T2	4		T3	30
values[0x0]	2225662	1			T1	11		T2	33		T3	12
values[0x1]	2588887	1			T1	2		T2	24		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	348789	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6180184

1

T1

11

T2

53

T3

28

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25830	1			T4	1		T53	2		T19	293
valid_sources[0x01]	25646	1			T4	1		T7	1		T8	4
valid_sources[0x02]	23639	1			T4	4		T7	2		T24	1
valid_sources[0x03]	23832	1			T4	1		T12	2		T24	2
valid_sources[0x04]	23733	1			T1	1		T7	1		T26	1
valid_sources[0x05]	26517	1			T18	6		T7	1		T15	3
valid_sources[0x06]	26278	1			T4	1		T18	3		T24	2
valid_sources[0x07]	26030	1			T2	2		T18	6		T24	1
valid_sources[0x08]	24328	1			T4	1		T16	1		T24	3
valid_sources[0x09]	24618	1			T2	1		T4	1		T24	3
valid_sources[0x0a]	26428	1			T4	1		T7	1		T22	1
valid_sources[0x0b]	25100	1			T4	3		T18	14		T7	1
valid_sources[0x0c]	26635	1			T2	2		T4	1		T12	1
valid_sources[0x0d]	26035	1			T4	2		T18	4		T53	1
valid_sources[0x0e]	27120	1			T4	3		T7	3		T12	7
valid_sources[0x0f]	26201	1			T4	2		T24	1		T53	3
valid_sources[0x10]	25978	1			T22	1		T19	279		T25	14
valid_sources[0x11]	23726	1			T4	1		T7	1		T26	1
valid_sources[0x12]	24993	1			T4	3		T22	1		T24	1
valid_sources[0x13]	27000	1			T18	2		T22	1		T24	1
valid_sources[0x14]	26875	1			T1	1		T4	1		T7	1
valid_sources[0x15]	26180	1			T4	1		T19	224		T29	4
valid_sources[0x16]	26827	1			T2	1		T8	4		T24	3
valid_sources[0x17]	26157	1			T18	17		T24	1		T15	1
valid_sources[0x18]	25917	1			T4	2		T19	281		T5	4
valid_sources[0x19]	25059	1			T4	1		T18	2		T53	1
valid_sources[0x1a]	24911	1			T18	2		T19	327		T28	17
valid_sources[0x1b]	24444	1			T7	1		T53	2		T19	242
valid_sources[0x1c]	25943	1			T2	2		T4	1		T22	1
valid_sources[0x1d]	25039	1			T18	3		T8	4		T22	1
valid_sources[0x1e]	24444	1			T4	1		T18	9		T24	1
valid_sources[0x1f]	24324	1			T2	1		T4	3		T53	2
valid_sources[0x20]	26081	1			T4	3		T18	1		T15	1
valid_sources[0x21]	24766	1			T7	1		T19	240		T55	7
valid_sources[0x22]	26413	1			T4	4		T22	1		T24	1
valid_sources[0x23]	25294	1			T4	2		T26	2		T24	2
valid_sources[0x24]	26365	1			T24	4		T19	232		T17	1
valid_sources[0x25]	24874	1			T18	7		T24	7		T19	207
valid_sources[0x26]	28309	1			T24	4		T53	2		T19	283
valid_sources[0x27]	25162	1			T4	1		T24	1		T53	1
valid_sources[0x28]	24798	1			T4	2		T18	1		T24	1
valid_sources[0x29]	23050	1			T1	1		T18	1		T24	1
valid_sources[0x2a]	26875	1			T4	1		T24	1		T19	247
valid_sources[0x2b]	25412	1			T4	3		T26	1		T24	3
valid_sources[0x2c]	24643	1			T4	2		T22	2		T19	254
valid_sources[0x2d]	26452	1			T4	1		T18	21		T22	1
valid_sources[0x2e]	27425	1			T4	2		T24	2		T19	305
valid_sources[0x2f]	25747	1			T4	1		T18	2		T24	5
valid_sources[0x30]	24368	1			T18	20		T19	300		T29	6
valid_sources[0x31]	24457	1			T18	5		T19	297		T17	1
valid_sources[0x32]	25719	1			T4	2		T18	3		T7	1
valid_sources[0x33]	24769	1			T4	2		T18	1		T16	42
valid_sources[0x34]	26865	1			T1	1		T22	1		T19	304
valid_sources[0x35]	23473	1			T4	1		T24	1		T53	1
valid_sources[0x36]	24810	1			T16	1		T53	1		T19	289
valid_sources[0x37]	24597	1			T4	1		T26	1		T22	1
valid_sources[0x38]	24785	1			T4	2		T18	26		T8	7
valid_sources[0x39]	23542	1			T4	1		T18	9		T53	1
valid_sources[0x3a]	25082	1			T18	2		T7	1		T22	1
valid_sources[0x3b]	26420	1			T18	3		T26	1		T19	212
valid_sources[0x3c]	25937	1			T4	4		T24	3		T53	1
valid_sources[0x3d]	25203	1			T4	4		T7	1		T24	2
valid_sources[0x3e]	26136	1			T4	1		T15	1		T19	265
valid_sources[0x3f]	26420	1			T4	1		T18	4		T24	3
valid_sources[0x40]	22392	1			T18	5		T53	2		T15	1
valid_sources[0x41]	24798	1			T4	2		T18	17		T22	2
valid_sources[0x42]	24101	1			T4	1		T7	1		T16	2
valid_sources[0x43]	25341	1			T7	2		T24	1		T53	1
valid_sources[0x44]	26049	1			T4	3		T18	18		T24	1
valid_sources[0x45]	24557	1			T1	1		T4	2		T7	1
valid_sources[0x46]	26860	1			T24	4		T19	297		T28	51
valid_sources[0x47]	25564	1			T2	1		T4	1		T19	297
valid_sources[0x48]	24495	1			T18	40		T26	4		T24	1
valid_sources[0x49]	25556	1			T4	1		T18	3		T26	1
valid_sources[0x4a]	25365	1			T2	1		T4	2		T22	1
valid_sources[0x4b]	24202	1			T8	4		T19	213		T55	2
valid_sources[0x4c]	24715	1			T18	2		T22	2		T19	244
valid_sources[0x4d]	25280	1			T4	3		T18	1		T24	2
valid_sources[0x4e]	24888	1			T2	1		T18	42		T19	314
valid_sources[0x4f]	24808	1			T4	2		T24	1		T53	1
valid_sources[0x50]	24477	1			T4	1		T26	2		T19	252
valid_sources[0x51]	24328	1			T8	1		T24	2		T19	230
valid_sources[0x52]	26982	1			T4	2		T18	16		T26	3
valid_sources[0x53]	26038	1			T4	2		T18	1		T24	3
valid_sources[0x54]	25510	1			T4	1		T18	1		T7	1
valid_sources[0x55]	24734	1			T4	1		T7	1		T19	295
valid_sources[0x56]	25617	1			T4	1		T24	1		T53	1
valid_sources[0x57]	25413	1			T1	1		T4	1		T18	5
valid_sources[0x58]	24518	1			T2	2		T4	1		T7	1
valid_sources[0x59]	25084	1			T4	1		T18	10		T24	1
valid_sources[0x5a]	27263	1			T4	1		T18	6		T7	1
valid_sources[0x5b]	24822	1			T4	2		T19	239		T25	6
valid_sources[0x5c]	26584	1			T18	4		T26	5		T24	1
valid_sources[0x5d]	26738	1			T4	1		T18	13		T19	287
valid_sources[0x5e]	24045	1			T26	1		T24	3		T53	1
valid_sources[0x5f]	27269	1			T4	1		T18	28		T24	1
valid_sources[0x60]	25287	1			T4	1		T18	4		T7	1
valid_sources[0x61]	27833	1			T3	10		T4	1		T18	19
valid_sources[0x62]	25219	1			T2	1		T4	1		T18	13
valid_sources[0x63]	26163	1			T2	1		T18	13		T22	3
valid_sources[0x64]	25378	1			T2	3		T24	1		T15	2
valid_sources[0x65]	25925	1			T24	3		T15	2		T19	313
valid_sources[0x66]	27992	1			T4	1		T26	2		T24	1
valid_sources[0x67]	28237	1			T2	3		T18	3		T22	2
valid_sources[0x68]	24954	1			T7	1		T19	240		T25	4
valid_sources[0x69]	25939	1			T18	11		T24	2		T53	1
valid_sources[0x6a]	24970	1			T4	1		T24	1		T19	264
valid_sources[0x6b]	24917	1			T4	3		T18	19		T24	2
valid_sources[0x6c]	23643	1			T4	2		T18	17		T7	3
valid_sources[0x6d]	24531	1			T18	3		T7	1		T12	49
valid_sources[0x6e]	26641	1			T4	1		T18	11		T24	3
valid_sources[0x6f]	24667	1			T4	1		T22	1		T24	1
valid_sources[0x70]	25199	1			T4	1		T18	2		T26	2
valid_sources[0x71]	26172	1			T4	1		T18	5		T53	1
valid_sources[0x72]	27399	1			T2	1		T4	1		T26	2
valid_sources[0x73]	24513	1			T4	1		T18	3		T7	1
valid_sources[0x74]	24275	1			T19	230		T29	1		T33	3
valid_sources[0x75]	27994	1			T4	1		T18	4		T7	1
valid_sources[0x76]	28326	1			T18	2		T24	1		T19	250
valid_sources[0x77]	25408	1			T18	11		T24	1		T19	282
valid_sources[0x78]	27703	1			T4	2		T18	7		T7	1
valid_sources[0x79]	25701	1			T4	1		T18	8		T53	1
valid_sources[0x7a]	25616	1			T4	1		T7	1		T22	2
valid_sources[0x7b]	26064	1			T53	1		T15	4		T19	272
valid_sources[0x7c]	24057	1			T4	1		T7	1		T24	2
valid_sources[0x7d]	25582	1			T18	12		T24	2		T53	1
valid_sources[0x7e]	24568	1			T4	1		T18	4		T24	2
valid_sources[0x7f]	25925	1			T3	10		T4	5		T19	300
valid_sources[0x80]	25064	1			T18	4		T22	1		T24	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1464481

1

T2

1

T3

8

T4

22

values[0x0]

all_enables

biggest_size

2179318

1

T1

7

T2

30

T3

6

values[0x1]

all_enables

biggest_size

2172894

1

T1

1

T2

17

T3

8