Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2750	1			T4	1		T18	12		T7	7
non_zero_bins[1]	2028	1			T18	4		T8	3		T12	3
zero	9584	1			T1	6		T3	7		T4	7

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	531	1			T18	3		T19	16		T23	1
uni	3844	1			T3	1		T4	3		T18	12
gen	4551	1			T1	3		T3	3		T4	2
res	852	1			T18	2		T7	2		T8	7
ins	4584	1			T1	3		T3	3		T4	3

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9547

1

T1

3

T3

4

T4

4

mubi_true

4815

1

T1

3

T3

3

T4

4

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

20

1

T36

1

T142

1

T277

1

pass

14342

1

T1

6

T3

7

T4

8

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	129	1			T18	1		T19	3		T20	2
upd	non_zero_bins[0]	pass	mubi_true	108	1			T18	1		T19	1		T20	3
upd	non_zero_bins[1]	pass	mubi_false	95	1			T19	5		T126	1		T21	3
upd	non_zero_bins[1]	pass	mubi_true	86	1			T19	2		T23	1		T20	1
upd	zero	pass	mubi_false	63	1			T19	4		T55	1		T20	2
upd	zero	pass	mubi_true	50	1			T18	1		T19	1		T123	1
uni	zero	pass	mubi_false	2821	1			T3	1		T4	1		T18	11
uni	zero	pass	mubi_true	1023	1			T4	2		T18	1		T19	19
gen	non_zero_bins[0]	pass	mubi_false	518	1			T18	4		T7	1		T8	4
gen	non_zero_bins[0]	pass	mubi_true	521	1			T7	3		T53	1		T15	4
gen	non_zero_bins[1]	pass	mubi_false	401	1			T19	10		T28	3		T278	1
gen	non_zero_bins[1]	pass	mubi_true	363	1			T18	2		T24	1		T19	11
gen	zero	fail	mubi_false	18	1			T36	1		T277	1		T143	1
gen	zero	pass	mubi_false	2004	1			T1	1		T3	1		T4	1
gen	zero	pass	mubi_true	726	1			T1	2		T3	2		T4	1
res	non_zero_bins[0]	pass	mubi_false	198	1			T18	2		T7	2		T19	2
res	non_zero_bins[0]	pass	mubi_true	188	1			T22	1		T24	1		T19	4
res	non_zero_bins[1]	pass	mubi_false	139	1			T8	3		T12	1		T19	2
res	non_zero_bins[1]	pass	mubi_true	140	1			T12	2		T26	1		T15	2
res	zero	fail	mubi_false	2	1			T142	1		T279	1		-	-
res	zero	pass	mubi_false	117	1			T8	4		T19	2		T21	2
res	zero	pass	mubi_true	68	1			T19	2		T121	1		T224	1
ins	non_zero_bins[0]	pass	mubi_false	561	1			T4	1		T18	3		T7	1
ins	non_zero_bins[0]	pass	mubi_true	527	1			T18	1		T8	1		T12	1
ins	non_zero_bins[1]	pass	mubi_false	411	1			T18	2		T22	1		T24	1
ins	non_zero_bins[1]	pass	mubi_true	393	1			T19	12		T32	1		T29	1
ins	zero	pass	mubi_false	2070	1			T1	2		T3	2		T4	1
ins	zero	pass	mubi_true	622	1			T1	1		T3	1		T4	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded