Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T16,T68
1	1	Covered	T1,T3,T16

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T18
1	0	Covered	T2,T8,T12
1	1	Covered	T2,T7,T8

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T16,T17
1	0	Covered	T1,T2,T5

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T3,T16,T17
1	Covered	T1,T2,T5

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T3,T16,T17
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T7,T8,T12
AutoCaptGenCnt	143	Covered	T7,T8,T12
AutoCaptReseedCnt	141	Covered	T7,T8,T12
AutoDispatch	125	Covered	T7,T8,T12
AutoFirstAckWait	119	Covered	T7,T8,T12
AutoLoadIns	69	Covered	T2,T7,T8
AutoSendGenCmd	150	Covered	T7,T8,T12
AutoSendReseedCmd	162	Covered	T7,T8,T12
BootDone	98	Covered	T1,T3,T16
BootGenAckWait	90	Covered	T1,T3,T16
BootInsAckWait	80	Covered	T1,T3,T16
BootLoadGen	85	Covered	T1,T3,T16
BootLoadIns	65	Covered	T1,T3,T16
BootLoadUni	102	Covered	T3,T24,T53
BootPulse	94	Covered	T1,T3,T16
BootUniAckWait	107	Covered	T3,T24,T53
Error	188	Covered	T1,T2,T5
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T3,T16,T17
SWPortMode	74	Covered	T3,T4,T18

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T7,T8,T12
AutoAckWait->Error	188	Covered	T145,T146,T147
AutoAckWait->Idle	211	Covered	T8,T12,T26
AutoAckWait->RejectCsrngEntropy	188	Covered	T135,T36,T133
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T7,T8,T12
AutoCaptGenCnt->Error	188	Covered	T115,T148
AutoCaptGenCnt->Idle	211	Covered	T8,T78,T113
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T132,T134,T149
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T7,T8,T12
AutoCaptReseedCnt->Error	188	Covered	T150,T151,T152
AutoCaptReseedCnt->Idle	211	Covered	T153,T154,T155
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T156,T157,T158
AutoDispatch->AutoCaptGenCnt	143	Covered	T7,T8,T12
AutoDispatch->AutoCaptReseedCnt	141	Covered	T7,T8,T12
AutoDispatch->Error	188	Covered	T107,T159
AutoDispatch->Idle	138	Covered	T7,T15,T28
AutoDispatch->RejectCsrngEntropy	188	Covered	T129,T122,T160
AutoFirstAckWait->AutoDispatch	125	Covered	T7,T8,T12
AutoFirstAckWait->Error	188	Covered	T85,T43
AutoFirstAckWait->Idle	211	Covered	T26,T65,T161
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T124,T162,T163
AutoLoadIns->AutoFirstAckWait	119	Covered	T7,T8,T12
AutoLoadIns->Error	188	Covered	T2,T6,T42
AutoLoadIns->Idle	211	Covered	T2,T22,T35
AutoLoadIns->RejectCsrngEntropy	188	Covered	T136,T130,T164
AutoSendGenCmd->AutoAckWait	156	Covered	T7,T8,T12
AutoSendGenCmd->Error	188	Covered	T5,T165,T166
AutoSendGenCmd->Idle	211	Covered	T12,T167,T106
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T17,T128,T168
AutoSendReseedCmd->AutoAckWait	168	Covered	T7,T8,T12
AutoSendReseedCmd->Error	188	Covered	T137
AutoSendReseedCmd->Idle	211	Covered	T169,T170,T171
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T142,T172,T173
BootDone->BootLoadUni	102	Covered	T3,T24,T53
BootDone->Error	188	Covered	T174,T175
BootDone->Idle	211	Covered	T176,T177,T178
BootDone->RejectCsrngEntropy	188	Covered	T16,T51,T68
BootGenAckWait->BootPulse	94	Covered	T1,T3,T16
BootGenAckWait->Error	188	Covered	T39,T179,T88
BootGenAckWait->Idle	211	Covered	T1,T39,T180
BootGenAckWait->RejectCsrngEntropy	188	Covered	T3,T143,T181
BootInsAckWait->BootLoadGen	85	Covered	T1,T3,T16
BootInsAckWait->Error	188	Covered	T182,T183,T184
BootInsAckWait->Idle	211	Covered	T41,T182,T111
BootInsAckWait->RejectCsrngEntropy	188	Covered	T185,T186,T187
BootLoadGen->BootGenAckWait	90	Covered	T1,T3,T16
BootLoadGen->Error	188	Covered	T41,T102
BootLoadGen->Idle	211	Covered	T69,T86,T104
BootLoadGen->RejectCsrngEntropy	188	Covered	T131,T188,T189
BootLoadIns->BootInsAckWait	80	Covered	T1,T3,T16
BootLoadIns->Error	188	Covered	T190,T191,T192
BootLoadIns->Idle	211	Covered	T193,T194,T195
BootLoadIns->RejectCsrngEntropy	188	Covered	T125,T196,T197
BootLoadUni->BootUniAckWait	107	Covered	T3,T24,T53
BootLoadUni->Error	188	Covered	T111
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T198,T199,T200
BootPulse->BootDone	98	Covered	T1,T3,T16
BootPulse->Error	188	Not Covered
BootPulse->Idle	211	Covered	T201,T202,T203
BootPulse->RejectCsrngEntropy	188	Covered	T204,T205,T206
BootUniAckWait->Error	188	Covered	T103,T207
BootUniAckWait->Idle	112	Covered	T3,T24,T53
BootUniAckWait->RejectCsrngEntropy	188	Covered	T141,T139,T208
Idle->AutoLoadIns	69	Covered	T2,T7,T8
Idle->BootLoadIns	65	Covered	T1,T3,T16
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T124,T142,T125
Idle->SWPortMode	74	Covered	T3,T4,T18
RejectCsrngEntropy->Error	188	Covered	T96,T209,T210
RejectCsrngEntropy->Idle	211	Covered	T3,T16,T17
SWPortMode->Error	188	Covered	T58,T59,T60
SWPortMode->Idle	211	Covered	T3,T4,T18
SWPortMode->RejectCsrngEntropy	188	Covered	T3,T16,T17

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T8
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T18
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T24,T53
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T3,T16
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T53
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T3,T24,T53
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T24,T53
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T8,T12
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T7,T8
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T7,T8,T12
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T7,T8,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T8,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T7,T8,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T7,T15,T28
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T7,T8,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T7,T8,T12
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T8,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T7,T8,T12
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T12
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T8,T12
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T7,T8,T12
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T18
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T16,T17
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T116,T117

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T2,T5
1	0	1	-	Not Covered
1	0	0	-	Covered	T3,T16,T17
0	-	-	1	Covered	T1,T2,T3
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	238419330	84873	0	0
FpvSecCmErrorStEscalate_A	238419330	84997	0	0
u_state_regs_A	238385244	238280402	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	84873	0	0
T1	2132	589	0	0
T2	914	333	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1080	0	0
T6	0	1124	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1102	0	0
T14	0	388	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	608	0	0
T58	0	320	0	0
T59	0	1085	0	0
T60	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	84997	0	0
T1	2132	590	0	0
T2	914	334	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1081	0	0
T6	0	1125	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1103	0	0
T14	0	389	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	609	0	0
T58	0	321	0	0
T59	0	1086	0	0
T60	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238385244	238280402	0	0
T1	963	814	0	0
T2	729	585	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0