Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	95.71	100.00	100.00		78.57	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	90.44			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T4,T18
DataWait	75	Covered	T1,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T83,T84
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T4,T18
DataWait->AckPls	80	Covered	T3,T4,T18
DataWait->Disabled	107	Covered	T8,T12,T78
DataWait->Error	99	Covered	T1,T85,T39
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T4,T22,T35
EndPointClear->Error	99	Covered	T2,T6,T42
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T4
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T5,T58

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T4,T18
Idle	-	1	0	-	Covered	T1,T3,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T4,T18
DataWait	-	-	-	0	Covered	T1,T3,T4
AckPls	-	-	-	-	Covered	T3,T4,T18
Error	-	-	-	-	Covered	T1,T2,T5
default	-	-	-	-	Covered	T2,T5,T58

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1668935310	606911	0	0
FpvSecCmErrorStEscalate_A	1668935310	607779	0	0
u_state_regs_A	1668901224	1668167330	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668935310	606911	0	0
T1	14924	4473	0	0
T2	6398	2281	0	0
T3	18844	0	0	0
T4	27328	0	0	0
T5	0	7510	0	0
T6	0	7868	0	0
T7	47250	0	0	0
T8	17731	0	0	0
T12	13888	0	0	0
T13	0	7714	0	0
T14	0	2716	0	0
T16	15645	0	0	0
T18	128674	0	0	0
T26	9058	0	0	0
T37	0	4256	0	0
T58	0	2190	0	0
T59	0	7545	0	0
T60	0	4080	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668935310	607779	0	0
T1	14924	4480	0	0
T2	6398	2288	0	0
T3	18844	0	0	0
T4	27328	0	0	0
T5	0	7517	0	0
T6	0	7875	0	0
T7	47250	0	0	0
T8	17731	0	0	0
T12	13888	0	0	0
T13	0	7721	0	0
T14	0	2723	0	0
T16	15645	0	0	0
T18	128674	0	0	0
T26	9058	0	0	0
T37	0	4263	0	0
T58	0	2197	0	0
T59	0	7552	0	0
T60	0	4087	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1668901224	1668167330	0	0
T1	13755	12712	0	0
T2	6213	5205	0	0
T3	18844	18389	0	0
T4	27328	26425	0	0
T7	47250	46753	0	0
T8	17731	17164	0	0
T12	13888	13503	0	0
T16	15645	15155	0	0
T18	128674	124264	0	0
T26	9058	8456	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T12,T22,T23
DataWait	75	Covered	T12,T22,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T12,T22,T23
DataWait->AckPls	80	Covered	T12,T22,T23
DataWait->Disabled	107	Covered	T12,T86,T87
DataWait->Error	99	Covered	T85,T88,T89
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T4,T22,T35
EndPointClear->Error	99	Covered	T2,T6,T42
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T12,T22,T23
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T5,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T12,T22,T23
Idle	-	1	0	-	Covered	T12,T22,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T12,T22,T23
DataWait	-	-	-	0	Covered	T12,T22,T23
AckPls	-	-	-	-	Covered	T12,T22,T23
Error	-	-	-	-	Covered	T1,T2,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238419330	86973	0	0
FpvSecCmErrorStEscalate_A	238419330	87097	0	0
u_state_regs_A	238419330	238314488	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	86973	0	0
T1	2132	639	0	0
T2	914	333	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1080	0	0
T6	0	1124	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1102	0	0
T14	0	388	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	608	0	0
T58	0	320	0	0
T59	0	1085	0	0
T60	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87097	0	0
T1	2132	640	0	0
T2	914	334	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1081	0	0
T6	0	1125	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1103	0	0
T14	0	389	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	609	0	0
T58	0	321	0	0
T59	0	1086	0	0
T60	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T16,T12,T24
DataWait	75	Covered	T16,T12,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T16,T12,T24
DataWait->AckPls	80	Covered	T16,T12,T24
DataWait->Disabled	107	Covered	T90,T91,T92
DataWait->Error	99	Covered	T5,T93,T94
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T4,T22,T35
EndPointClear->Error	99	Covered	T2,T6,T42
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T16,T12,T24
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T58,T59

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T16,T12,T24
Idle	-	1	0	-	Covered	T16,T12,T24
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T16,T12,T24
DataWait	-	-	-	0	Covered	T16,T12,T24
AckPls	-	-	-	-	Covered	T16,T12,T24
Error	-	-	-	-	Covered	T1,T2,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238419330	86973	0	0
FpvSecCmErrorStEscalate_A	238419330	87097	0	0
u_state_regs_A	238419330	238314488	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	86973	0	0
T1	2132	639	0	0
T2	914	333	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1080	0	0
T6	0	1124	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1102	0	0
T14	0	388	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	608	0	0
T58	0	320	0	0
T59	0	1085	0	0
T60	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87097	0	0
T1	2132	640	0	0
T2	914	334	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1081	0	0
T6	0	1125	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1103	0	0
T14	0	389	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	609	0	0
T58	0	321	0	0
T59	0	1086	0	0
T60	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T8,T23,T25
DataWait	75	Covered	T8,T23,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T8,T23,T25
DataWait->AckPls	80	Covered	T8,T23,T25
DataWait->Disabled	107	Covered	T8,T95
DataWait->Error	99	Covered	T96,T97,T98
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T4,T22,T35
EndPointClear->Error	99	Covered	T2,T6,T42
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T8,T23,T25
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T5,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T8,T23,T25
Idle	-	1	0	-	Covered	T8,T23,T25
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T8,T23,T25
DataWait	-	-	-	0	Covered	T8,T23,T25
AckPls	-	-	-	-	Covered	T8,T23,T25
Error	-	-	-	-	Covered	T1,T2,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238419330	86973	0	0
FpvSecCmErrorStEscalate_A	238419330	87097	0	0
u_state_regs_A	238419330	238314488	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	86973	0	0
T1	2132	639	0	0
T2	914	333	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1080	0	0
T6	0	1124	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1102	0	0
T14	0	388	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	608	0	0
T58	0	320	0	0
T59	0	1085	0	0
T60	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87097	0	0
T1	2132	640	0	0
T2	914	334	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1081	0	0
T6	0	1125	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1103	0	0
T14	0	389	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	609	0	0
T58	0	321	0	0
T59	0	1086	0	0
T60	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T26,T27,T23
DataWait	75	Covered	T26,T27,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T26,T27,T23
DataWait->AckPls	80	Covered	T26,T27,T23
DataWait->Disabled	107	Covered	T99,T100,T101
DataWait->Error	99	Covered	T43,T102,T103
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T4,T22,T35
EndPointClear->Error	99	Covered	T2,T6,T42
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T26,T27,T23
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T5,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T26,T27,T23
Idle	-	1	0	-	Covered	T26,T27,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T26,T27,T23
DataWait	-	-	-	0	Covered	T26,T27,T23
AckPls	-	-	-	-	Covered	T26,T27,T23
Error	-	-	-	-	Covered	T1,T2,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238419330	86973	0	0
FpvSecCmErrorStEscalate_A	238419330	87097	0	0
u_state_regs_A	238419330	238314488	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	86973	0	0
T1	2132	639	0	0
T2	914	333	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1080	0	0
T6	0	1124	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1102	0	0
T14	0	388	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	608	0	0
T58	0	320	0	0
T59	0	1085	0	0
T60	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87097	0	0
T1	2132	640	0	0
T2	914	334	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1081	0	0
T6	0	1125	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1103	0	0
T14	0	389	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	609	0	0
T58	0	321	0	0
T59	0	1086	0	0
T60	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T28,T25
DataWait	75	Covered	T23,T28,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T28,T25
DataWait->AckPls	80	Covered	T23,T28,T25
DataWait->Disabled	107	Covered	T104,T105,T106
DataWait->Error	99	Covered	T41,T107,T108
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T4,T22,T35
EndPointClear->Error	99	Covered	T2,T6,T42
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T28,T25
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T5,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T28,T25
Idle	-	1	0	-	Covered	T23,T28,T25
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T28,T25
DataWait	-	-	-	0	Covered	T23,T28,T25
AckPls	-	-	-	-	Covered	T23,T28,T25
Error	-	-	-	-	Covered	T1,T2,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238419330	86973	0	0
FpvSecCmErrorStEscalate_A	238419330	87097	0	0
u_state_regs_A	238419330	238314488	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	86973	0	0
T1	2132	639	0	0
T2	914	333	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1080	0	0
T6	0	1124	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1102	0	0
T14	0	388	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	608	0	0
T58	0	320	0	0
T59	0	1085	0	0
T60	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87097	0	0
T1	2132	640	0	0
T2	914	334	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1081	0	0
T6	0	1125	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1103	0	0
T14	0	389	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	609	0	0
T58	0	321	0	0
T59	0	1086	0	0
T60	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T4,T18
DataWait	75	Covered	T3,T4,T18
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T83
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T4,T18
DataWait->AckPls	80	Covered	T3,T4,T18
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T109,T110,T111
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T4,T22,T35
EndPointClear->Error	99	Covered	T6,T42,T112
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T4,T18
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T13,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T4,T18
Idle	-	1	0	-	Covered	T3,T4,T18
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T4,T18
DataWait	-	-	-	0	Covered	T3,T4,T18
AckPls	-	-	-	-	Covered	T3,T4,T18
Error	-	-	-	-	Covered	T1,T2,T5
default	-	-	-	-	Covered	T2,T5,T58

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238419330	85073	0	0
FpvSecCmErrorStEscalate_A	238419330	85197	0	0
u_state_regs_A	238385244	238280402	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	85073	0	0
T1	2132	639	0	0
T2	914	283	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1030	0	0
T6	0	1124	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1102	0	0
T14	0	388	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	608	0	0
T58	0	270	0	0
T59	0	1035	0	0
T60	0	540	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	85197	0	0
T1	2132	640	0	0
T2	914	284	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1031	0	0
T6	0	1125	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1103	0	0
T14	0	389	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	609	0	0
T58	0	271	0	0
T59	0	1036	0	0
T60	0	541	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238385244	238280402	0	0
T1	963	814	0	0
T2	729	585	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T8,T24,T15
DataWait	75	Covered	T1,T8,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T84
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T8,T24,T15
DataWait->AckPls	80	Covered	T8,T24,T15
DataWait->Disabled	107	Covered	T78,T113,T114
DataWait->Error	99	Covered	T1,T39,T115
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T4,T22,T35
EndPointClear->Error	99	Covered	T2,T6,T42
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T8,T24
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T5,T58,T59

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T8,T24,T15
Idle	-	1	0	-	Covered	T1,T8,T24
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T8,T24,T15
DataWait	-	-	-	0	Covered	T1,T8,T24
AckPls	-	-	-	-	Covered	T8,T24,T15
Error	-	-	-	-	Covered	T1,T2,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238419330	86973	0	0
FpvSecCmErrorStEscalate_A	238419330	87097	0	0
u_state_regs_A	238419330	238314488	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	86973	0	0
T1	2132	639	0	0
T2	914	333	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1080	0	0
T6	0	1124	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1102	0	0
T14	0	388	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	608	0	0
T58	0	320	0	0
T59	0	1085	0	0
T60	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	87097	0	0
T1	2132	640	0	0
T2	914	334	0	0
T3	2692	0	0	0
T4	3904	0	0	0
T5	0	1081	0	0
T6	0	1125	0	0
T7	6750	0	0	0
T8	2533	0	0	0
T12	1984	0	0	0
T13	0	1103	0	0
T14	0	389	0	0
T16	2235	0	0	0
T18	18382	0	0	0
T26	1294	0	0	0
T37	0	609	0	0
T58	0	321	0	0
T59	0	1086	0	0
T60	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238419330	238314488	0	0
T1	2132	1983	0	0
T2	914	770	0	0
T3	2692	2627	0	0
T4	3904	3775	0	0
T7	6750	6679	0	0
T8	2533	2452	0	0
T12	1984	1929	0	0
T16	2235	2165	0	0
T18	18382	17752	0	0
T26	1294	1208	0	0