Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.12 100.00 86.49 94.12 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 90.44 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 96.36 100.00 91.30 94.12 100.00



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.12 100.00 86.49 94.12 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 90.44 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 96.36 100.00 91.30 94.12 100.00

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T7,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT75,T76,T77
110Not Covered
111CoveredT1,T2,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT44,T73,T74
101CoveredT1,T2,T7
110Not Covered
111CoveredT7,T8,T12

Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataKnown_A 476476720 642044 0 0
DepthKnown_A 476838660 476628976 0 0
RvalidKnown_A 476838660 476628976 0 0
WreadyKnown_A 476838660 476628976 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 476838660 728387 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 476476720 642044 0 0
T2 394 83 0 0
T3 5384 0 0 0
T4 7808 0 0 0
T7 13500 10499 0 0
T8 5066 2697 0 0
T12 3968 2546 0 0
T15 0 1901 0 0
T16 4470 0 0 0
T17 0 364 0 0
T18 36764 0 0 0
T22 5366 3471 0 0
T25 0 9930 0 0
T26 2588 1576 0 0
T28 0 10797 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 476838660 476628976 0 0
T1 4264 3966 0 0
T2 1828 1540 0 0
T3 5384 5254 0 0
T4 7808 7550 0 0
T7 13500 13358 0 0
T8 5066 4904 0 0
T12 3968 3858 0 0
T16 4470 4330 0 0
T18 36764 35504 0 0
T26 2588 2416 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 476838660 476628976 0 0
T1 4264 3966 0 0
T2 1828 1540 0 0
T3 5384 5254 0 0
T4 7808 7550 0 0
T7 13500 13358 0 0
T8 5066 4904 0 0
T12 3968 3858 0 0
T16 4470 4330 0 0
T18 36764 35504 0 0
T26 2588 2416 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 476838660 476628976 0 0
T1 4264 3966 0 0
T2 1828 1540 0 0
T3 5384 5254 0 0
T4 7808 7550 0 0
T7 13500 13358 0 0
T8 5066 4904 0 0
T12 3968 3858 0 0
T16 4470 4330 0 0
T18 36764 35504 0 0
T26 2588 2416 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 476838660 728387 0 0
T1 4264 2254 0 0
T2 1828 742 0 0
T3 5384 0 0 0
T4 7808 0 0 0
T7 13500 10499 0 0
T8 5066 2697 0 0
T12 3968 2546 0 0
T15 0 1901 0 0
T16 4470 0 0 0
T17 0 364 0 0
T18 36764 0 0 0
T22 0 3471 0 0
T26 2588 1576 0 0
T28 0 10797 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT29,T65,T78
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT77
110Not Covered
111CoveredT1,T2,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT44,T73,T79
101CoveredT1,T2,T7
110Not Covered
111CoveredT7,T8,T12

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataKnown_A 238238360 315143 0 0
DepthKnown_A 238419330 238314488 0 0
RvalidKnown_A 238419330 238314488 0 0
WreadyKnown_A 238419330 238314488 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 238419330 357867 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238238360 315143 0 0
T2 197 16 0 0
T3 2692 0 0 0
T4 3904 0 0 0
T7 6750 5241 0 0
T8 2533 1276 0 0
T12 1984 1268 0 0
T15 0 938 0 0
T16 2235 0 0 0
T17 0 241 0 0
T18 18382 0 0 0
T22 2683 1669 0 0
T25 0 4938 0 0
T26 1294 772 0 0
T28 0 5392 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238419330 238314488 0 0
T1 2132 1983 0 0
T2 914 770 0 0
T3 2692 2627 0 0
T4 3904 3775 0 0
T7 6750 6679 0 0
T8 2533 2452 0 0
T12 1984 1929 0 0
T16 2235 2165 0 0
T18 18382 17752 0 0
T26 1294 1208 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238419330 238314488 0 0
T1 2132 1983 0 0
T2 914 770 0 0
T3 2692 2627 0 0
T4 3904 3775 0 0
T7 6750 6679 0 0
T8 2533 2452 0 0
T12 1984 1929 0 0
T16 2235 2165 0 0
T18 18382 17752 0 0
T26 1294 1208 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238419330 238314488 0 0
T1 2132 1983 0 0
T2 914 770 0 0
T3 2692 2627 0 0
T4 3904 3775 0 0
T7 6750 6679 0 0
T8 2533 2452 0 0
T12 1984 1929 0 0
T16 2235 2165 0 0
T18 18382 17752 0 0
T26 1294 1208 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 238419330 357867 0 0
T1 2132 1130 0 0
T2 914 344 0 0
T3 2692 0 0 0
T4 3904 0 0 0
T7 6750 5241 0 0
T8 2533 1276 0 0
T12 1984 1268 0 0
T15 0 938 0 0
T16 2235 0 0 0
T17 0 241 0 0
T18 18382 0 0 0
T22 0 1669 0 0
T26 1294 772 0 0
T28 0 5392 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T7,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT75,T76,T80
110Not Covered
111CoveredT1,T2,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT74,T81,T82
101CoveredT1,T2,T7
110Not Covered
111CoveredT7,T8,T12

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataKnown_A 238238360 326901 0 0
DepthKnown_A 238419330 238314488 0 0
RvalidKnown_A 238419330 238314488 0 0
WreadyKnown_A 238419330 238314488 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 238419330 370520 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238238360 326901 0 0
T2 197 67 0 0
T3 2692 0 0 0
T4 3904 0 0 0
T7 6750 5258 0 0
T8 2533 1421 0 0
T12 1984 1278 0 0
T15 0 963 0 0
T16 2235 0 0 0
T17 0 123 0 0
T18 18382 0 0 0
T22 2683 1802 0 0
T25 0 4992 0 0
T26 1294 804 0 0
T28 0 5405 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238419330 238314488 0 0
T1 2132 1983 0 0
T2 914 770 0 0
T3 2692 2627 0 0
T4 3904 3775 0 0
T7 6750 6679 0 0
T8 2533 2452 0 0
T12 1984 1929 0 0
T16 2235 2165 0 0
T18 18382 17752 0 0
T26 1294 1208 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238419330 238314488 0 0
T1 2132 1983 0 0
T2 914 770 0 0
T3 2692 2627 0 0
T4 3904 3775 0 0
T7 6750 6679 0 0
T8 2533 2452 0 0
T12 1984 1929 0 0
T16 2235 2165 0 0
T18 18382 17752 0 0
T26 1294 1208 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238419330 238314488 0 0
T1 2132 1983 0 0
T2 914 770 0 0
T3 2692 2627 0 0
T4 3904 3775 0 0
T7 6750 6679 0 0
T8 2533 2452 0 0
T12 1984 1929 0 0
T16 2235 2165 0 0
T18 18382 17752 0 0
T26 1294 1208 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 238419330 370520 0 0
T1 2132 1124 0 0
T2 914 398 0 0
T3 2692 0 0 0
T4 3904 0 0 0
T7 6750 5258 0 0
T8 2533 1421 0 0
T12 1984 1278 0 0
T15 0 963 0 0
T16 2235 0 0 0
T17 0 123 0 0
T18 18382 0 0 0
T22 0 1802 0 0
T26 1294 804 0 0
T28 0 5405 0 0