Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	633742	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5093359

1

T1

30

T2

25

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1516443	1			T1	61		T2	39		T3	37
values[0x0]	1949210	1			T1	19		T2	14		T3	14
values[0x1]	2261448	1			T1	12		T2	12		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	314852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5412249

1

T1

52

T2

33

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23661	1			T40	3		T27	1		T41	4
valid_sources[0x01]	22908	1			T40	1		T41	6		T64	1
valid_sources[0x02]	20010	1			T31	2		T40	10		T41	8
valid_sources[0x03]	22773	1			T14	1		T41	1		T63	5
valid_sources[0x04]	22761	1			T3	1		T10	1		T4	1
valid_sources[0x05]	23105	1			T10	1		T6	13		T31	1
valid_sources[0x06]	21455	1			T1	1		T41	4		T32	1
valid_sources[0x07]	23538	1			T40	2		T41	4		T18	1
valid_sources[0x08]	22233	1			T3	4		T14	1		T40	1
valid_sources[0x09]	23256	1			T27	7		T41	4		T61	1
valid_sources[0x0a]	21557	1			T5	2		T27	5		T41	1
valid_sources[0x0b]	20418	1			T1	1		T4	2		T31	1
valid_sources[0x0c]	22713	1			T1	1		T40	3		T41	3
valid_sources[0x0d]	21920	1			T4	1		T31	1		T40	4
valid_sources[0x0e]	22544	1			T31	1		T41	1		T18	1
valid_sources[0x0f]	22921	1			T10	1		T27	5		T52	5
valid_sources[0x10]	20638	1			T14	1		T40	7		T41	3
valid_sources[0x11]	22618	1			T31	1		T14	1		T40	3
valid_sources[0x12]	21810	1			T31	1		T14	1		T40	1
valid_sources[0x13]	22226	1			T1	2		T40	10		T41	7
valid_sources[0x14]	25121	1			T1	1		T40	3		T41	2
valid_sources[0x15]	21568	1			T41	2		T9	1		T22	2
valid_sources[0x16]	22263	1			T10	1		T40	1		T41	5
valid_sources[0x17]	22011	1			T10	1		T31	1		T27	2
valid_sources[0x18]	22117	1			T5	1		T40	7		T41	4
valid_sources[0x19]	19597	1			T40	1		T41	4		T63	2
valid_sources[0x1a]	22166	1			T41	2		T22	4		T12	1
valid_sources[0x1b]	23932	1			T2	1		T31	2		T40	2
valid_sources[0x1c]	20907	1			T1	2		T40	5		T41	3
valid_sources[0x1d]	20895	1			T10	1		T41	2		T61	1
valid_sources[0x1e]	24400	1			T1	1		T10	1		T5	2
valid_sources[0x1f]	22967	1			T10	1		T41	1		T64	1
valid_sources[0x20]	22211	1			T1	2		T40	1		T41	3
valid_sources[0x21]	22005	1			T40	1		T41	4		T18	1
valid_sources[0x22]	25810	1			T41	3		T18	2		T63	1
valid_sources[0x23]	22848	1			T1	1		T41	4		T63	2
valid_sources[0x24]	22685	1			T1	1		T10	1		T31	1
valid_sources[0x25]	22656	1			T1	1		T40	5		T41	7
valid_sources[0x26]	21805	1			T1	1		T31	1		T40	6
valid_sources[0x27]	20911	1			T40	2		T41	3		T64	1
valid_sources[0x28]	23602	1			T40	2		T27	1		T41	2
valid_sources[0x29]	21513	1			T31	1		T40	2		T41	2
valid_sources[0x2a]	23036	1			T10	2		T31	1		T40	5
valid_sources[0x2b]	22934	1			T40	1		T62	1		T22	2
valid_sources[0x2c]	22743	1			T4	1		T31	2		T41	2
valid_sources[0x2d]	21859	1			T1	1		T2	6		T40	1
valid_sources[0x2e]	22559	1			T1	1		T3	1		T10	1
valid_sources[0x2f]	20094	1			T40	7		T41	1		T53	3
valid_sources[0x30]	23282	1			T1	1		T40	7		T41	1
valid_sources[0x31]	20886	1			T3	3		T40	2		T41	3
valid_sources[0x32]	22720	1			T40	1		T41	3		T146	1
valid_sources[0x33]	23972	1			T1	1		T3	2		T40	2
valid_sources[0x34]	22906	1			T1	2		T40	6		T41	4
valid_sources[0x35]	20344	1			T1	1		T40	9		T41	2
valid_sources[0x36]	22579	1			T10	1		T40	3		T41	1
valid_sources[0x37]	23306	1			T27	3		T41	3		T60	1
valid_sources[0x38]	22546	1			T4	1		T31	2		T41	3
valid_sources[0x39]	23706	1			T14	1		T40	2		T41	3
valid_sources[0x3a]	21788	1			T6	101		T40	5		T41	5
valid_sources[0x3b]	21806	1			T3	5		T6	3		T41	5
valid_sources[0x3c]	22455	1			T41	2		T60	1		T34	1
valid_sources[0x3d]	22242	1			T1	1		T3	1		T31	1
valid_sources[0x3e]	20916	1			T10	1		T40	9		T41	5
valid_sources[0x3f]	25500	1			T31	1		T40	2		T41	1
valid_sources[0x40]	23326	1			T31	1		T14	1		T40	8
valid_sources[0x41]	23090	1			T1	4		T4	1		T31	1
valid_sources[0x42]	22935	1			T1	1		T6	27		T31	1
valid_sources[0x43]	21339	1			T6	88		T41	1		T59	1
valid_sources[0x44]	20793	1			T31	1		T14	1		T41	2
valid_sources[0x45]	22938	1			T31	1		T14	2		T41	3
valid_sources[0x46]	23501	1			T40	2		T41	2		T18	2
valid_sources[0x47]	23382	1			T5	1		T40	1		T27	1
valid_sources[0x48]	23350	1			T1	1		T40	5		T41	8
valid_sources[0x49]	22165	1			T10	1		T4	1		T41	1
valid_sources[0x4a]	21313	1			T4	1		T5	1		T40	5
valid_sources[0x4b]	23580	1			T31	2		T14	2		T40	7
valid_sources[0x4c]	22531	1			T1	1		T40	3		T41	7
valid_sources[0x4d]	24110	1			T10	1		T14	1		T40	1
valid_sources[0x4e]	21502	1			T1	1		T5	1		T40	1
valid_sources[0x4f]	23003	1			T1	1		T2	13		T10	2
valid_sources[0x50]	21474	1			T10	1		T31	1		T40	6
valid_sources[0x51]	22574	1			T41	2		T11	1		T36	1
valid_sources[0x52]	20874	1			T5	1		T31	1		T40	5
valid_sources[0x53]	21622	1			T2	1		T10	1		T40	7
valid_sources[0x54]	21252	1			T40	1		T27	1		T41	5
valid_sources[0x55]	23533	1			T1	1		T14	1		T27	1
valid_sources[0x56]	22350	1			T31	1		T40	3		T41	4
valid_sources[0x57]	21914	1			T1	1		T10	1		T14	2
valid_sources[0x58]	22561	1			T10	1		T14	1		T41	4
valid_sources[0x59]	20047	1			T1	3		T10	3		T31	1
valid_sources[0x5a]	24239	1			T10	2		T40	2		T18	1
valid_sources[0x5b]	22163	1			T31	1		T14	1		T40	2
valid_sources[0x5c]	23550	1			T40	6		T41	5		T60	1
valid_sources[0x5d]	21030	1			T40	2		T41	5		T60	1
valid_sources[0x5e]	20641	1			T41	1		T49	2		T22	4
valid_sources[0x5f]	23685	1			T14	1		T40	4		T41	1
valid_sources[0x60]	24184	1			T10	1		T40	2		T41	2
valid_sources[0x61]	22182	1			T1	1		T27	16		T41	2
valid_sources[0x62]	22817	1			T40	1		T41	2		T63	2
valid_sources[0x63]	22805	1			T1	1		T31	1		T14	1
valid_sources[0x64]	23064	1			T40	1		T27	5		T41	3
valid_sources[0x65]	21395	1			T27	3		T41	4		T18	1
valid_sources[0x66]	23100	1			T1	2		T10	3		T6	12
valid_sources[0x67]	21733	1			T10	1		T41	1		T32	4
valid_sources[0x68]	21574	1			T10	2		T40	4		T41	3
valid_sources[0x69]	22863	1			T10	1		T40	12		T62	2
valid_sources[0x6a]	20347	1			T10	1		T5	1		T6	2
valid_sources[0x6b]	24249	1			T1	2		T2	3		T31	1
valid_sources[0x6c]	22976	1			T6	42		T14	1		T40	2
valid_sources[0x6d]	23042	1			T40	2		T41	4		T49	1
valid_sources[0x6e]	22847	1			T40	2		T41	4		T62	2
valid_sources[0x6f]	21177	1			T10	1		T31	1		T14	1
valid_sources[0x70]	21221	1			T1	1		T14	1		T40	3
valid_sources[0x71]	22666	1			T1	1		T41	1		T49	1
valid_sources[0x72]	21368	1			T40	1		T27	6		T41	2
valid_sources[0x73]	21527	1			T1	2		T3	2		T31	1
valid_sources[0x74]	20184	1			T4	1		T5	1		T31	2
valid_sources[0x75]	23437	1			T40	4		T41	4		T49	1
valid_sources[0x76]	22101	1			T1	1		T10	1		T40	2
valid_sources[0x77]	22254	1			T40	12		T41	1		T18	1
valid_sources[0x78]	22848	1			T3	1		T40	4		T41	1
valid_sources[0x79]	23374	1			T31	1		T40	5		T27	7
valid_sources[0x7a]	22482	1			T31	1		T40	2		T64	1
valid_sources[0x7b]	22352	1			T5	3		T14	1		T41	7
valid_sources[0x7c]	21476	1			T10	1		T31	1		T40	3
valid_sources[0x7d]	21695	1			T1	1		T5	1		T41	4
valid_sources[0x7e]	22673	1			T31	1		T60	1		T49	3
valid_sources[0x7f]	24655	1			T1	1		T40	1		T41	5
valid_sources[0x80]	22789	1			T10	1		T31	1		T41	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1280997

1

T1

3

T2

11

T3

12

values[0x0]

all_enables

biggest_size

1908557

1

T1

17

T2

8

T3

6

values[0x1]

all_enables

biggest_size

1903805

1

T1

10

T2

6

T3

9