Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
62.50 62.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 62.50 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
62.50 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 52 24 28 53.85


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 24 28 53.85 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
non_zero_bins[0] 2516 1 T1 1 T6 9 T31 1
non_zero_bins[1] 1710 1 T1 2 T6 5 T31 1
zero 8536 1 T1 1 T2 5 T3 6



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd 473 1 T6 4 T27 1 T41 3
uni 3336 1 T1 1 T6 10 T31 2
gen 4114 1 T1 1 T2 3 T3 3
res 781 1 T1 1 T3 1 T6 2
ins 4058 1 T1 1 T2 2 T3 2



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
mubi_false 8432 1 T1 2 T2 2 T3 3
mubi_true 4330 1 T1 2 T2 3 T3 3



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 21 1 T2 1 T14 1 T59 1
pass 12741 1 T1 4 T2 4 T3 6



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 52 24 28 53.85 24
Automatically Generated Cross Bins 52 24 28 53.85 24
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] * [fail] * -- -- 6
[uni] [zero] [fail] * -- -- 2
[gen , res] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 8
[ins] * [fail] * -- -- 6


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[gen , res] [zero] [fail] [mubi_true] -- -- 2


Covered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd non_zero_bins[0] pass mubi_false 114 1 T6 2 T28 1 T32 1
upd non_zero_bins[0] pass mubi_true 104 1 T34 1 T23 1 T175 1
upd non_zero_bins[1] pass mubi_false 78 1 T6 1 T27 1 T41 1
upd non_zero_bins[1] pass mubi_true 71 1 T6 1 T41 1 T26 1
upd zero pass mubi_false 45 1 T41 1 T281 1 T187 1
upd zero pass mubi_true 61 1 T23 2 T178 1 T282 1
uni zero pass mubi_false 2501 1 T1 1 T6 7 T31 2
uni zero pass mubi_true 835 1 T6 3 T40 2 T41 1
gen non_zero_bins[0] pass mubi_false 547 1 T6 1 T40 1 T41 2
gen non_zero_bins[0] pass mubi_true 433 1 T6 1 T31 1 T40 1
gen non_zero_bins[1] pass mubi_false 320 1 T6 1 T52 1 T22 1
gen non_zero_bins[1] pass mubi_true 328 1 T1 1 T40 1 T41 1
gen zero fail mubi_false 19 1 T2 1 T14 1 T59 1
gen zero pass mubi_false 1725 1 T3 1 T4 1 T5 1
gen zero pass mubi_true 742 1 T2 2 T3 2 T10 2
res non_zero_bins[0] pass mubi_false 173 1 T41 1 T18 2 T55 2
res non_zero_bins[0] pass mubi_true 193 1 T22 2 T281 1 T23 1
res non_zero_bins[1] pass mubi_false 104 1 T40 1 T55 1 T23 1
res non_zero_bins[1] pass mubi_true 121 1 T1 1 T6 1 T31 1
res zero fail mubi_false 2 1 T39 1 T133 1 - -
res zero pass mubi_false 110 1 T3 1 T33 1 T11 2
res zero pass mubi_true 78 1 T6 1 T12 2 T24 1
ins non_zero_bins[0] pass mubi_false 482 1 T1 1 T6 2 T40 2
ins non_zero_bins[0] pass mubi_true 470 1 T6 3 T40 1 T18 1
ins non_zero_bins[1] pass mubi_false 356 1 T6 1 T40 1 T27 1
ins non_zero_bins[1] pass mubi_true 332 1 T40 1 T41 1 T52 1
ins zero pass mubi_false 1856 1 T2 1 T3 1 T10 1
ins zero pass mubi_true 562 1 T2 1 T3 1 T10 1


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded

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