Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.79	100.00	94.44		91.89	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	96.79	100.00	94.44		91.89	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.79	100.00	94.44		91.89	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.81	100.00	94.44		91.89	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.09	100.00	90.15			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T30,T29
1	1	Covered	T31,T27,T59

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T18,T8
1	1	Covered	T2,T3,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T10
1	0	Covered	T7,T8,T30

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T7,T8,T30

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T7,T8,T30

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	68	91.89
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T3,T14
AutoCaptGenCnt	143	Covered	T2,T3,T14
AutoCaptReseedCnt	141	Covered	T3,T18,T8
AutoDispatch	125	Covered	T2,T3,T14
AutoFirstAckWait	119	Covered	T2,T3,T14
AutoLoadIns	69	Covered	T2,T3,T10
AutoSendGenCmd	150	Covered	T2,T3,T14
AutoSendReseedCmd	162	Covered	T3,T18,T19
BootDone	98	Covered	T31,T27,T59
BootGenAckWait	90	Covered	T31,T27,T59
BootInsAckWait	80	Covered	T31,T27,T59
BootLoadGen	85	Covered	T31,T27,T59
BootLoadIns	65	Covered	T31,T27,T59
BootLoadUni	102	Covered	T31,T27,T59
BootPulse	94	Covered	T31,T27,T59
BootUniAckWait	107	Covered	T31,T27,T59
Error	188	Covered	T7,T8,T30
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T2,T3,T10
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T3,T18,T8
AutoAckWait->Error	188	Covered	T64,T92
AutoAckWait->Idle	211	Covered	T18,T19,T55
AutoAckWait->RejectCsrngEntropy	188	Covered	T2,T3,T14
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T3,T14
AutoCaptGenCnt->Error	188	Covered	T93,T94,T95
AutoCaptGenCnt->Idle	211	Covered	T96,T97,T98
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T67,T99,T100
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T3,T18,T19
AutoCaptReseedCnt->Error	188	Covered	T8,T101,T102
AutoCaptReseedCnt->Idle	211	Covered	T103,T104,T105
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T106,T107,T108
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T3,T14
AutoDispatch->AutoCaptReseedCnt	141	Covered	T3,T18,T8
AutoDispatch->Error	188	Covered	T7,T109,T110
AutoDispatch->Idle	138	Covered	T22,T11,T12
AutoDispatch->RejectCsrngEntropy	188	Covered	T75,T111,T112
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T3,T14
AutoFirstAckWait->Error	188	Not Covered
AutoFirstAckWait->Idle	211	Covered	T18,T113,T114
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T70,T73,T115
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T3,T14
AutoLoadIns->Error	188	Covered	T116,T117,T118
AutoLoadIns->Idle	211	Covered	T7,T8,T19
AutoLoadIns->RejectCsrngEntropy	188	Covered	T10,T119,T120
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T3,T14
AutoSendGenCmd->Error	188	Covered	T121,T122
AutoSendGenCmd->Idle	211	Covered	T55,T58,T123
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T124,T125,T126
AutoSendReseedCmd->AutoAckWait	168	Covered	T3,T18,T19
AutoSendReseedCmd->Error	188	Covered	T127,T128,T129
AutoSendReseedCmd->Idle	211	Covered	T130,T131,T132
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T33,T39,T133
BootDone->BootLoadUni	102	Covered	T31,T27,T59
BootDone->Error	188	Covered	T45,T134,T135
BootDone->Idle	211	Covered	T136,T137,T138
BootDone->RejectCsrngEntropy	188	Covered	T37,T139,T140
BootGenAckWait->BootPulse	94	Covered	T31,T27,T59
BootGenAckWait->Error	188	Covered	T141,T142
BootGenAckWait->Idle	211	Covered	T30,T65,T66
BootGenAckWait->RejectCsrngEntropy	188	Covered	T49,T50,T143
BootInsAckWait->BootLoadGen	85	Covered	T31,T27,T59
BootInsAckWait->Error	188	Covered	T30,T44,T144
BootInsAckWait->Idle	211	Covered	T16,T145,T44
BootInsAckWait->RejectCsrngEntropy	188	Covered	T51,T146,T78
BootLoadGen->BootGenAckWait	90	Covered	T31,T27,T59
BootLoadGen->Error	188	Not Covered
BootLoadGen->Idle	211	Covered	T147,T148,T149
BootLoadGen->RejectCsrngEntropy	188	Covered	T150,T151,T152
BootLoadIns->BootInsAckWait	80	Covered	T31,T27,T59
BootLoadIns->Error	188	Covered	T65,T16,T153
BootLoadIns->Idle	211	Covered	T154,T155,T156
BootLoadIns->RejectCsrngEntropy	188	Covered	T157,T158,T159
BootLoadUni->BootUniAckWait	107	Covered	T31,T27,T59
BootLoadUni->Error	188	Not Covered
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T80,T160,T161
BootPulse->BootDone	98	Covered	T31,T27,T59
BootPulse->Error	188	Not Covered
BootPulse->Idle	211	Covered	T29,T79,T162
BootPulse->RejectCsrngEntropy	188	Covered	T163,T164,T165
BootUniAckWait->Error	188	Covered	T166
BootUniAckWait->Idle	112	Covered	T31,T27,T59
BootUniAckWait->RejectCsrngEntropy	188	Covered	T71,T167,T168
Idle->AutoLoadIns	69	Covered	T2,T3,T10
Idle->BootLoadIns	65	Covered	T31,T27,T59
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T2,T3,T37
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T169,T170,T171
RejectCsrngEntropy->Idle	211	Covered	T2,T3,T10
SWPortMode->Error	188	Covered	T15,T17,T42
SWPortMode->Idle	211	Covered	T2,T3,T10
SWPortMode->RejectCsrngEntropy	188	Covered	T10,T14,T59

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T27,T59
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T27,T59
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T31,T27,T59
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T31,T27,T59
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T27,T59
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T31,T27,T59
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T31,T27,T59
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T27,T59
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T27,T59
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T59,T30,T29
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T27,T59
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T31,T27,T38
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T31,T27,T59
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T3,T14
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T3,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T3,T14
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T3,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T3,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T22,T11,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T3,T18,T8
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T3,T14
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T3,T18,T19
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T8
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T18,T19
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T18,T19,T33
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T30
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T66,T172

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T7,T8,T30
1	0	1	-	Not Covered
1	0	0	-	Covered	T2,T3,T10
0	-	-	1	Covered	T2,T3,T10
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	191926264	83259	0	0
FpvSecCmErrorStEscalate_A	191926264	83395	0	0
u_state_regs_A	191885774	191781399	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	83259	0	0
T7	819	242	0	0
T8	0	1153	0	0
T9	0	587	0	0
T15	0	420	0	0
T16	0	743	0	0
T17	0	348	0	0
T18	2761	0	0	0
T26	3590	0	0	0
T27	3308	0	0	0
T28	3040	0	0	0
T30	0	388	0	0
T41	20807	0	0	0
T59	1660	0	0	0
T60	1303	0	0	0
T61	1582	0	0	0
T62	1102	0	0	0
T64	0	619	0	0
T65	0	405	0	0
T66	0	1103	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	83395	0	0
T7	819	243	0	0
T8	0	1154	0	0
T9	0	588	0	0
T15	0	421	0	0
T16	0	744	0	0
T17	0	349	0	0
T18	2761	0	0	0
T26	3590	0	0	0
T27	3308	0	0	0
T28	3040	0	0	0
T30	0	389	0	0
T41	20807	0	0	0
T59	1660	0	0	0
T60	1303	0	0	0
T61	1582	0	0	0
T62	1102	0	0	0
T64	0	620	0	0
T65	0	406	0	0
T66	0	1104	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191885774	191781399	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2077	1938	0	0
T5	679	519	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0