Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.58	100.00	83.78	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.09	100.00	90.15			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.58	100.00	83.78	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.09	100.00	90.15			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T18,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T86
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T83,T89
1	0	1	Covered	T2,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	383502108	641997	0	0
DepthKnown_A	383852528	383643778	0	0
RvalidKnown_A	383852528	383643778	0	0
WreadyKnown_A	383852528	383643778	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	383852528	733455	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383502108	641997	0	0
T2	5072	539	0	0
T3	4178	561	0	0
T4	936	0	0	0
T5	604	0	0	0
T6	29024	0	0	0
T7	370	95	0	0
T8	0	296	0	0
T10	4240	400	0	0
T14	5808	679	0	0
T18	0	3785	0	0
T19	0	2668	0	0
T31	6706	0	0	0
T33	0	495	0	0
T40	25922	0	0	0
T59	0	335	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383852528	383643778	0	0
T1	5414	5312	0	0
T2	5072	4906	0	0
T3	4178	3992	0	0
T4	4282	4004	0	0
T5	1464	1144	0	0
T6	29024	28348	0	0
T10	4240	4064	0	0
T14	5808	5642	0	0
T31	6706	6572	0	0
T40	25922	25024	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383852528	383643778	0	0
T1	5414	5312	0	0
T2	5072	4906	0	0
T3	4178	3992	0	0
T4	4282	4004	0	0
T5	1464	1144	0	0
T6	29024	28348	0	0
T10	4240	4064	0	0
T14	5808	5642	0	0
T31	6706	6572	0	0
T40	25922	25024	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383852528	383643778	0	0
T1	5414	5312	0	0
T2	5072	4906	0	0
T3	4178	3992	0	0
T4	4282	4004	0	0
T5	1464	1144	0	0
T6	29024	28348	0	0
T10	4240	4064	0	0
T14	5808	5642	0	0
T31	6706	6572	0	0
T40	25922	25024	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	383852528	733455	0	0
T2	5072	539	0	0
T3	4178	561	0	0
T4	4282	0	0	0
T5	1464	0	0	0
T6	29024	0	0	0
T7	1638	750	0	0
T8	0	2504	0	0
T10	4240	400	0	0
T14	5808	679	0	0
T18	0	3785	0	0
T19	0	2668	0	0
T30	0	278	0	0
T31	6706	0	0	0
T40	25922	0	0	0
T59	0	335	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T21,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T83,T89
1	0	1	Covered	T2,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T3,T18,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	191751054	315852	0	0
DepthKnown_A	191926264	191821889	0	0
RvalidKnown_A	191926264	191821889	0	0
WreadyKnown_A	191926264	191821889	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	191926264	361371	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191751054	315852	0	0
T2	2536	273	0	0
T3	2089	283	0	0
T4	468	0	0	0
T5	302	0	0	0
T6	14512	0	0	0
T7	185	11	0	0
T8	0	112	0	0
T10	2120	207	0	0
T14	2904	345	0	0
T18	0	1841	0	0
T19	0	1322	0	0
T31	3353	0	0	0
T33	0	166	0	0
T40	12961	0	0	0
T59	0	169	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	361371	0	0
T2	2536	273	0	0
T3	2089	283	0	0
T4	2141	0	0	0
T5	732	0	0	0
T6	14512	0	0	0
T7	819	311	0	0
T8	0	1221	0	0
T10	2120	207	0	0
T14	2904	345	0	0
T18	0	1841	0	0
T19	0	1322	0	0
T30	0	141	0	0
T31	3353	0	0	0
T40	12961	0	0	0
T59	0	169	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T18,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T86
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	191751054	326145	0	0
DepthKnown_A	191926264	191821889	0	0
RvalidKnown_A	191926264	191821889	0	0
WreadyKnown_A	191926264	191821889	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	191926264	372084	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191751054	326145	0	0
T2	2536	266	0	0
T3	2089	278	0	0
T4	468	0	0	0
T5	302	0	0	0
T6	14512	0	0	0
T7	185	84	0	0
T8	0	184	0	0
T10	2120	193	0	0
T14	2904	334	0	0
T18	0	1944	0	0
T19	0	1346	0	0
T31	3353	0	0	0
T33	0	329	0	0
T40	12961	0	0	0
T59	0	166	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	191821889	0	0
T1	2707	2656	0	0
T2	2536	2453	0	0
T3	2089	1996	0	0
T4	2141	2002	0	0
T5	732	572	0	0
T6	14512	14174	0	0
T10	2120	2032	0	0
T14	2904	2821	0	0
T31	3353	3286	0	0
T40	12961	12512	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	191926264	372084	0	0
T2	2536	266	0	0
T3	2089	278	0	0
T4	2141	0	0	0
T5	732	0	0	0
T6	14512	0	0	0
T7	819	439	0	0
T8	0	1283	0	0
T10	2120	193	0	0
T14	2904	334	0	0
T18	0	1944	0	0
T19	0	1346	0	0
T30	0	137	0	0
T31	3353	0	0	0
T40	12961	0	0	0
T59	0	166	0	0