Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.97			55.97

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_count_max_reqs_cntr	17.82			17.82
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr	94.12			94.12
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr	94.12			94.12
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr	94.12			94.12
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr	94.12			94.12

---

Module Instance : tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
17.82			17.82

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
17.82			17.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.09	100.00	90.15			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.10	100.00	91.30			100.00		gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.10	100.00	91.30			100.00		gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.10	100.00	91.30			100.00		gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.10	100.00	91.30			100.00		gen_normal_fifo.u_fifo_cnt

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=32,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
17.82	17.82

tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	202	36	17.82
Total Bits 0->1	101	20	19.80
Total Bits 1->0	101	16	15.84

Ports	8	5	62.50
Port Bits	202	36	17.82
Port Bits 0->1	101	20	19.80
Port Bits 1->0	101	16	15.84

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[0]	Yes	Yes	*T7,*T8,*T9	Yes	T2,T3,T10	INPUT
set_cnt_i[4:1]	No	No		Yes	T11,T12,T13	INPUT
set_cnt_i[31:5]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	*T2,*T3,*T14	Yes	T2,T3,T10	OUTPUT
cnt_o[31:5]	No	No		No		OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	*T2,*T3,*T14	Yes	T2,T3,T10	OUTPUT
cnt_after_commit_o[31:5]	No	No		No		OUTPUT
err_o	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT

*Tests covering at least one bit in the range

---

Toggle Coverage for Module : prim_count ( parameter Width=5,ResetValue=0,EnableAlertTriggerSVA=1,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
94.12	94.12

tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORE	TOGGLE
94.12	94.12

tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORE	TOGGLE
94.12	94.12

tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORE	TOGGLE
94.12	94.12

tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

	Total	Covered	Percent
Totals	9	8	88.89
Total Bits	34	32	94.12
Total Bits 0->1	17	16	94.12
Total Bits 1->0	17	16	94.12

Ports	9	8	88.89
Port Bits	34	32	94.12
Port Bits 0->1	17	16	94.12
Port Bits 1->0	17	16	94.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T7,T18,T8	Yes	T7,T18,T8	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T7,T18,T8	Yes	T7,T18,T8	INPUT
incr_en_i	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	202	36	17.82
Total Bits 0->1	101	20	19.80
Total Bits 1->0	101	16	15.84

Ports	8	5	62.50
Port Bits	202	36	17.82
Port Bits 0->1	101	20	19.80
Port Bits 1->0	101	16	15.84

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[0]	Yes	Yes	*T7,*T8,*T9	Yes	T2,T3,T10	INPUT
set_cnt_i[4:1]	No	No		Yes	T11,T12,T13	INPUT
set_cnt_i[31:5]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	*T2,*T3,*T14	Yes	T2,T3,T10	OUTPUT
cnt_o[31:5]	No	No		No		OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	*T2,*T3,*T14	Yes	T2,T3,T10	OUTPUT
cnt_after_commit_o[31:5]	No	No		No		OUTPUT
err_o	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

	Total	Covered	Percent
Totals	9	8	88.89
Total Bits	34	32	94.12
Total Bits 0->1	17	16	94.12
Total Bits 1->0	17	16	94.12

Ports	9	8	88.89
Port Bits	34	32	94.12
Port Bits 0->1	17	16	94.12
Port Bits 1->0	17	16	94.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T18,T19,T9	Yes	T18,T19,T9	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T18,T19,T9	Yes	T18,T19,T9	INPUT
incr_en_i	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

	Total	Covered	Percent
Totals	9	8	88.89
Total Bits	34	32	94.12
Total Bits 0->1	17	16	94.12
Total Bits 1->0	17	16	94.12

Ports	9	8	88.89
Port Bits	34	32	94.12
Port Bits 0->1	17	16	94.12
Port Bits 1->0	17	16	94.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
incr_en_i	Yes	Yes	T3,T18,T8	Yes	T3,T18,T8	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T3,T18,T19	Yes	T3,T18,T19	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T3,T18,T8	Yes	T3,T18,T8	OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

	Total	Covered	Percent
Totals	9	8	88.89
Total Bits	34	32	94.12
Total Bits 0->1	17	16	94.12
Total Bits 1->0	17	16	94.12

Ports	9	8	88.89
Port Bits	34	32	94.12
Port Bits 0->1	17	16	94.12
Port Bits 1->0	17	16	94.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T7,T18,T8	Yes	T7,T18,T8	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T7,T18,T8	Yes	T7,T18,T8	INPUT
incr_en_i	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

	Total	Covered	Percent
Totals	9	8	88.89
Total Bits	34	32	94.12
Total Bits 0->1	17	16	94.12
Total Bits 1->0	17	16	94.12

Ports	9	8	88.89
Port Bits	34	32	94.12
Port Bits 0->1	17	16	94.12
Port Bits 1->0	17	16	94.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T18,T19,T22	Yes	T18,T19,T22	INPUT
set_cnt_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4]	Yes	Yes	T18,T19,T22	Yes	T18,T19,T22	INPUT
incr_en_i	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
cnt_after_commit_o[4:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	OUTPUT
err_o	No	No		No		OUTPUT