Group : tb.dut.u_edn_cov_if::edn_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cfg_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cfg_cg 100.00 1 100 1 64 64




Group Instance : edn_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 21 0 21 100.00


Variables for Group Instance edn_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 0 3 100.00 100 1 1 0
cp_num_boot_reqs 2 0 2 100.00 100 1 1 0
cp_num_endpoints 7 0 7 100.00 100 1 1 8


Crosses for Group Instance edn_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_num_endpoints_mode 21 0 21 100.00 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
both 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
boot_req_mode 153 1 T1 1 T22 1 T23 1
auto_req_mode 133 1 T7 1 T11 1 T15 1
sw_mode 2650 1 T40 1 T49 1 T54 1



Summary for Variable cp_num_boot_reqs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 301 1 T7 1 T22 1 T48 1
single 99 1 T1 1 T23 1 T16 1



Summary for Variable cp_num_endpoints

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1610 1 T40 1 T48 1 T49 1
auto[2] 101 1 T27 1 T297 1 T231 7
auto[3] 152 1 T298 1 T299 1 T300 1
auto[4] 71 1 T63 1 T101 14 T301 1
auto[5] 86 1 T31 1 T30 1 T60 1
auto[6] 77 1 T1 1 T58 1 T62 1
auto[7] 839 1 T7 1 T22 1 T23 1



Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 21 0 21 100.00


Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins
cp_num_endpointscp_modeCOUNTSTATUS
[auto[0]] [boot_req_mode , auto_req_mode , sw_mode] -- Excluded (3 bins)


Covered bins
cp_num_endpointscp_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] boot_req_mode 97 1 T48 1 T87 1 T33 1
auto[1] auto_req_mode 86 1 T11 1 T15 1 T17 1
auto[1] sw_mode 1427 1 T40 1 T49 1 T54 1
auto[2] boot_req_mode 1 1 T302 1 - - - -
auto[2] auto_req_mode 4 1 T27 1 T303 1 T304 1
auto[2] sw_mode 96 1 T297 1 T231 7 T305 1
auto[3] boot_req_mode 6 1 T298 1 T306 1 T307 1
auto[3] auto_req_mode 4 1 T299 1 T300 1 T308 1
auto[3] sw_mode 142 1 T309 1 T310 71 T311 69
auto[4] boot_req_mode 7 1 T63 1 T312 1 T313 1
auto[4] auto_req_mode 2 1 T301 1 T314 1 - -
auto[4] sw_mode 62 1 T101 14 T315 1 T316 1
auto[5] boot_req_mode 4 1 T30 1 T60 1 T317 1
auto[5] auto_req_mode 4 1 T318 1 T319 1 T320 1
auto[5] sw_mode 78 1 T31 1 T90 43 T321 1
auto[6] boot_req_mode 2 1 T1 1 T322 1 - -
auto[6] auto_req_mode 2 1 T323 1 T324 1 - -
auto[6] sw_mode 73 1 T58 1 T62 1 T67 1
auto[7] boot_req_mode 36 1 T22 1 T23 1 T24 1
auto[7] auto_req_mode 31 1 T7 1 T16 1 T28 1
auto[7] sw_mode 772 1 T32 1 T25 1 T39 6

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