Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	675226	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5559170

1

T1

20

T2

55

T3

46

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1637406	1			T1	93		T2	5		T3	34
values[0x0]	2125451	1			T1	8		T2	30		T3	25
values[0x1]	2471539	1			T1	11		T2	34		T3	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	331200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5903196

1

T1

48

T2

60

T3

55

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22392	1			T2	1		T48	1		T5	323
valid_sources[0x01]	23053	1			T3	3		T40	2		T24	4
valid_sources[0x02]	23385	1			T3	3		T24	1		T5	10
valid_sources[0x03]	25324	1			T49	1		T54	2		T24	1
valid_sources[0x04]	26219	1			T5	110		T20	215		T12	1
valid_sources[0x05]	24283	1			T48	1		T49	2		T24	1
valid_sources[0x06]	23240	1			T5	165		T20	219		T39	2
valid_sources[0x07]	25513	1			T54	1		T5	5		T20	207
valid_sources[0x08]	23376	1			T11	2		T5	165		T20	243
valid_sources[0x09]	23644	1			T18	9		T24	1		T5	517
valid_sources[0x0a]	24499	1			T49	1		T5	175		T20	211
valid_sources[0x0b]	22804	1			T5	58		T20	222		T6	2
valid_sources[0x0c]	25406	1			T48	1		T5	80		T20	236
valid_sources[0x0d]	24154	1			T48	2		T54	1		T5	217
valid_sources[0x0e]	23604	1			T5	52		T20	213		T12	1
valid_sources[0x0f]	23614	1			T49	1		T5	797		T20	234
valid_sources[0x10]	24915	1			T3	3		T48	3		T24	1
valid_sources[0x11]	24096	1			T5	20		T20	234		T15	1
valid_sources[0x12]	24162	1			T48	3		T5	378		T20	208
valid_sources[0x13]	24025	1			T54	1		T5	439		T20	192
valid_sources[0x14]	23484	1			T2	1		T48	3		T24	2
valid_sources[0x15]	26016	1			T48	2		T5	370		T20	228
valid_sources[0x16]	24528	1			T4	5		T24	1		T5	219
valid_sources[0x17]	23488	1			T48	3		T24	1		T5	399
valid_sources[0x18]	25061	1			T38	29		T48	1		T11	1
valid_sources[0x19]	25286	1			T5	208		T61	5		T20	193
valid_sources[0x1a]	23644	1			T48	5		T11	5		T5	355
valid_sources[0x1b]	23854	1			T48	1		T5	423		T20	215
valid_sources[0x1c]	23667	1			T2	2		T5	358		T20	191
valid_sources[0x1d]	23144	1			T5	256		T20	222		T41	20
valid_sources[0x1e]	23932	1			T2	1		T40	1		T48	3
valid_sources[0x1f]	22853	1			T5	76		T20	189		T88	1
valid_sources[0x20]	23045	1			T2	1		T5	393		T20	226
valid_sources[0x21]	26119	1			T2	1		T48	1		T5	281
valid_sources[0x22]	22391	1			T11	1		T5	29		T20	241
valid_sources[0x23]	24128	1			T2	1		T54	1		T5	282
valid_sources[0x24]	25346	1			T48	2		T49	1		T24	1
valid_sources[0x25]	23533	1			T24	1		T5	723		T20	245
valid_sources[0x26]	24712	1			T2	1		T5	255		T20	206
valid_sources[0x27]	25069	1			T2	1		T24	1		T5	95
valid_sources[0x28]	23842	1			T49	3		T50	3		T5	302
valid_sources[0x29]	22717	1			T5	52		T32	24		T20	203
valid_sources[0x2a]	25856	1			T18	1		T5	24		T20	190
valid_sources[0x2b]	24769	1			T40	1		T48	1		T24	1
valid_sources[0x2c]	24810	1			T24	2		T5	570		T20	231
valid_sources[0x2d]	22603	1			T48	1		T11	5		T54	1
valid_sources[0x2e]	24180	1			T2	3		T48	1		T11	5
valid_sources[0x2f]	23015	1			T3	2		T22	287		T48	1
valid_sources[0x30]	22981	1			T3	48		T48	1		T24	1
valid_sources[0x31]	23847	1			T48	4		T5	208		T20	239
valid_sources[0x32]	25681	1			T4	8		T40	1		T5	905
valid_sources[0x33]	24302	1			T11	1		T54	1		T5	204
valid_sources[0x34]	24772	1			T2	1		T5	16		T20	211
valid_sources[0x35]	24591	1			T18	5		T24	3		T5	17
valid_sources[0x36]	25007	1			T2	4		T48	8		T49	1
valid_sources[0x37]	23505	1			T24	4		T5	272		T32	13
valid_sources[0x38]	23979	1			T48	1		T54	1		T24	1
valid_sources[0x39]	24020	1			T40	1		T54	1		T5	272
valid_sources[0x3a]	24658	1			T48	4		T49	2		T24	2
valid_sources[0x3b]	24417	1			T48	4		T49	2		T24	1
valid_sources[0x3c]	24718	1			T5	248		T20	186		T39	2
valid_sources[0x3d]	24795	1			T48	1		T11	2		T5	639
valid_sources[0x3e]	23490	1			T5	495		T61	2		T32	4
valid_sources[0x3f]	25103	1			T18	6		T40	1		T48	2
valid_sources[0x40]	24903	1			T48	3		T5	239		T20	232
valid_sources[0x41]	25113	1			T18	4		T11	1		T24	1
valid_sources[0x42]	24545	1			T48	2		T49	1		T5	187
valid_sources[0x43]	25361	1			T48	2		T5	325		T20	196
valid_sources[0x44]	23412	1			T3	3		T5	433		T20	258
valid_sources[0x45]	23674	1			T18	4		T11	1		T24	1
valid_sources[0x46]	25255	1			T48	2		T24	1		T5	517
valid_sources[0x47]	24315	1			T23	169		T49	1		T24	2
valid_sources[0x48]	25388	1			T49	1		T24	2		T5	214
valid_sources[0x49]	24404	1			T40	3		T49	1		T24	1
valid_sources[0x4a]	24762	1			T48	3		T5	486		T20	253
valid_sources[0x4b]	24517	1			T48	2		T24	2		T5	37
valid_sources[0x4c]	24505	1			T2	1		T48	1		T24	1
valid_sources[0x4d]	24822	1			T5	588		T20	222		T39	4
valid_sources[0x4e]	25006	1			T4	27		T40	1		T49	2
valid_sources[0x4f]	24970	1			T5	319		T20	211		T15	3
valid_sources[0x50]	23987	1			T49	1		T5	133		T20	206
valid_sources[0x51]	23907	1			T5	663		T20	271		T16	2
valid_sources[0x52]	24005	1			T48	2		T54	1		T5	449
valid_sources[0x53]	21763	1			T49	1		T5	172		T20	209
valid_sources[0x54]	24622	1			T24	1		T5	244		T20	224
valid_sources[0x55]	23514	1			T1	112		T54	1		T24	1
valid_sources[0x56]	22505	1			T2	2		T5	288		T20	239
valid_sources[0x57]	22723	1			T3	7		T4	2		T11	1
valid_sources[0x58]	25439	1			T2	1		T49	1		T54	1
valid_sources[0x59]	25755	1			T49	1		T5	396		T20	213
valid_sources[0x5a]	25012	1			T48	1		T49	1		T54	1
valid_sources[0x5b]	23115	1			T48	10		T49	1		T5	55
valid_sources[0x5c]	24992	1			T5	130		T20	188		T55	2
valid_sources[0x5d]	25646	1			T3	1		T18	1		T40	1
valid_sources[0x5e]	23988	1			T49	1		T24	3		T5	237
valid_sources[0x5f]	24633	1			T5	154		T20	246		T12	1
valid_sources[0x60]	24865	1			T48	1		T24	2		T5	899
valid_sources[0x61]	22846	1			T24	2		T5	177		T20	203
valid_sources[0x62]	23889	1			T48	4		T54	1		T5	275
valid_sources[0x63]	22663	1			T48	1		T5	137		T20	194
valid_sources[0x64]	24429	1			T3	5		T11	2		T5	403
valid_sources[0x65]	25214	1			T24	2		T5	120		T20	236
valid_sources[0x66]	24095	1			T11	1		T54	1		T5	102
valid_sources[0x67]	24987	1			T40	1		T48	1		T5	325
valid_sources[0x68]	24813	1			T5	293		T20	239		T39	6
valid_sources[0x69]	26303	1			T2	1		T48	1		T49	1
valid_sources[0x6a]	22848	1			T11	6		T54	1		T5	238
valid_sources[0x6b]	23617	1			T2	2		T4	10		T18	2
valid_sources[0x6c]	25905	1			T24	1		T5	176		T20	205
valid_sources[0x6d]	24971	1			T40	1		T48	1		T5	158
valid_sources[0x6e]	24469	1			T11	1		T5	231		T32	3
valid_sources[0x6f]	26348	1			T24	1		T5	362		T20	206
valid_sources[0x70]	23581	1			T40	2		T24	1		T5	31
valid_sources[0x71]	23764	1			T48	1		T24	1		T5	380
valid_sources[0x72]	23596	1			T2	2		T7	161		T5	133
valid_sources[0x73]	23811	1			T2	1		T48	1		T24	1
valid_sources[0x74]	22905	1			T5	316		T20	218		T39	1
valid_sources[0x75]	25180	1			T40	1		T49	1		T24	2
valid_sources[0x76]	22736	1			T48	1		T49	1		T24	1
valid_sources[0x77]	23906	1			T48	1		T11	2		T5	162
valid_sources[0x78]	24960	1			T48	2		T24	1		T5	67
valid_sources[0x79]	26242	1			T48	1		T5	443		T20	233
valid_sources[0x7a]	22594	1			T11	2		T5	229		T20	220
valid_sources[0x7b]	24701	1			T3	3		T48	1		T5	361
valid_sources[0x7c]	24509	1			T48	2		T11	1		T5	172
valid_sources[0x7d]	23675	1			T2	2		T48	1		T5	30
valid_sources[0x7e]	23451	1			T2	1		T54	1		T24	1
valid_sources[0x7f]	24094	1			T2	1		T48	1		T24	1
valid_sources[0x80]	24653	1			T48	1		T5	220		T20	213

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1398731

1

T1

6

T2

1

T3

9

values[0x0]

all_enables

biggest_size

2081774

1

T1

4

T2

26

T3

19

values[0x1]

all_enables

biggest_size

2078665

1

T1

10

T2

28

T3

18