Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2524	1			T1	2		T7	4		T23	3
non_zero_bins[1]	1739	1			T22	1		T48	1		T11	1
zero	8831	1			T1	5		T2	2		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	482	1			T22	1		T23	1		T5	6
uni	3470	1			T1	2		T7	1		T22	2
gen	4138	1			T1	2		T2	1		T3	2
res	797	1			T1	1		T7	2		T11	2
ins	4207	1			T1	2		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8594

1

T1

4

T2

2

T3

1

mubi_true

4500

1

T1

3

T3

3

T7

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

17

1

T174

1

T165

1

T272

1

pass

13077

1

T1

7

T2

2

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	112	1			T23	1		T5	2		T30	1
upd	non_zero_bins[0]	pass	mubi_true	124	1			T5	3		T20	2		T21	1
upd	non_zero_bins[1]	pass	mubi_false	70	1			T20	3		T21	3		T90	1
upd	non_zero_bins[1]	pass	mubi_true	82	1			T22	1		T5	1		T20	3
upd	zero	pass	mubi_false	52	1			T21	1		T90	1		T91	1
upd	zero	pass	mubi_true	42	1			T87	1		T39	1		T217	1
uni	zero	pass	mubi_false	2581	1			T1	2		T7	1		T22	2
uni	zero	pass	mubi_true	889	1			T48	1		T49	1		T54	1
gen	non_zero_bins[0]	pass	mubi_false	476	1			T23	1		T11	3		T5	3
gen	non_zero_bins[0]	pass	mubi_true	434	1			T1	1		T7	1		T24	1
gen	non_zero_bins[1]	pass	mubi_false	332	1			T48	1		T5	4		T31	1
gen	non_zero_bins[1]	pass	mubi_true	317	1			T5	2		T20	3		T39	2
gen	zero	fail	mubi_false	15	1			T174	1		T272	1		T273	1
gen	zero	pass	mubi_false	1782	1			T2	1		T7	3		T22	1
gen	zero	pass	mubi_true	782	1			T1	1		T3	2		T22	1
res	non_zero_bins[0]	pass	mubi_false	197	1			T7	2		T5	2		T20	2
res	non_zero_bins[0]	pass	mubi_true	183	1			T1	1		T11	2		T5	1
res	non_zero_bins[1]	pass	mubi_false	112	1			T20	2		T34	1		T15	1
res	non_zero_bins[1]	pass	mubi_true	126	1			T21	1		T70	1		T90	1
res	zero	fail	mubi_false	2	1			T165	1		T166	1		-	-
res	zero	pass	mubi_false	94	1			T5	1		T20	2		T42	1
res	zero	pass	mubi_true	83	1			T20	1		T27	2		T28	2
ins	non_zero_bins[0]	pass	mubi_false	489	1			T7	1		T48	1		T5	5
ins	non_zero_bins[0]	pass	mubi_true	509	1			T23	1		T48	1		T5	5
ins	non_zero_bins[1]	pass	mubi_false	356	1			T11	1		T5	6		T20	3
ins	non_zero_bins[1]	pass	mubi_true	344	1			T24	1		T5	4		T32	1
ins	zero	pass	mubi_false	1924	1			T1	2		T2	1		T3	1
ins	zero	pass	mubi_true	585	1			T3	1		T22	1		T18	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded