Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T33,T35
1	1	Covered	T1,T3,T22

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T3,T4

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T18,T12
1	0	Covered	T2,T4,T6

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T3,T18,T12
1	Covered	T2,T4,T6

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T3,T18,T12
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T6

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T7,T11,T12
AutoCaptGenCnt	143	Covered	T2,T7,T11
AutoCaptReseedCnt	141	Covered	T7,T11,T15
AutoDispatch	125	Covered	T2,T7,T11
AutoFirstAckWait	119	Covered	T2,T7,T11
AutoLoadIns	69	Covered	T2,T3,T4
AutoSendGenCmd	150	Covered	T2,T7,T11
AutoSendReseedCmd	162	Covered	T7,T11,T15
BootDone	98	Covered	T1,T22,T18
BootGenAckWait	90	Covered	T1,T22,T18
BootInsAckWait	80	Covered	T1,T3,T22
BootLoadGen	85	Covered	T1,T22,T18
BootLoadIns	65	Covered	T1,T3,T22
BootLoadUni	102	Covered	T1,T22,T18
BootPulse	94	Covered	T1,T22,T18
BootUniAckWait	107	Covered	T1,T22,T18
Error	188	Covered	T2,T4,T6
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T3,T18,T12
SWPortMode	74	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T7,T11,T15
AutoAckWait->Error	188	Covered	T14,T131,T132
AutoAckWait->Idle	211	Covered	T15,T53,T98
AutoAckWait->RejectCsrngEntropy	188	Covered	T12,T133,T94
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T7,T11
AutoCaptGenCnt->Error	188	Covered	T120,T121,T110
AutoCaptGenCnt->Idle	211	Covered	T98,T103,T112
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T65,T134,T135
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T7,T11,T15
AutoCaptReseedCnt->Error	188	Covered	T136,T137,T138
AutoCaptReseedCnt->Idle	211	Covered	T139,T140,T141
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T68,T142,T143
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T7,T11
AutoDispatch->AutoCaptReseedCnt	141	Covered	T7,T11,T15
AutoDispatch->Error	188	Covered	T6,T46,T144
AutoDispatch->Idle	138	Covered	T7,T11,T16
AutoDispatch->RejectCsrngEntropy	188	Covered	T92,T145,T146
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T7,T11
AutoFirstAckWait->Error	188	Covered	T147,T148,T149
AutoFirstAckWait->Idle	211	Covered	T53,T150,T151
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T93,T152,T153
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T7,T11
AutoLoadIns->Error	188	Covered	T4,T154,T155
AutoLoadIns->Idle	211	Covered	T2,T3,T4
AutoLoadIns->RejectCsrngEntropy	188	Covered	T35,T64,T156
AutoSendGenCmd->AutoAckWait	156	Covered	T7,T11,T12
AutoSendGenCmd->Error	188	Covered	T2,T157
AutoSendGenCmd->Idle	211	Covered	T15,T111,T117
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T158,T159,T160
AutoSendReseedCmd->AutoAckWait	168	Covered	T7,T11,T15
AutoSendReseedCmd->Error	188	Covered	T42,T43,T161
AutoSendReseedCmd->Idle	211	Covered	T162,T163,T164
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T57,T165,T166
BootDone->BootLoadUni	102	Covered	T1,T22,T18
BootDone->Error	188	Covered	T109,T167
BootDone->Idle	211	Covered	T33,T168,T169
BootDone->RejectCsrngEntropy	188	Covered	T37,T170,T171
BootGenAckWait->BootPulse	94	Covered	T1,T22,T18
BootGenAckWait->Error	188	Covered	T83,T114,T172
BootGenAckWait->Idle	211	Covered	T41,T97,T119
BootGenAckWait->RejectCsrngEntropy	188	Covered	T66,T173,T174
BootInsAckWait->BootLoadGen	85	Covered	T1,T22,T18
BootInsAckWait->Error	188	Covered	T41,T175,T176
BootInsAckWait->Idle	211	Covered	T13,T83,T99
BootInsAckWait->RejectCsrngEntropy	188	Covered	T3,T18,T177
BootLoadGen->BootGenAckWait	90	Covered	T1,T22,T18
BootLoadGen->Error	188	Covered	T115
BootLoadGen->Idle	211	Covered	T178,T179,T180
BootLoadGen->RejectCsrngEntropy	188	Covered	T181,T182,T183
BootLoadIns->BootInsAckWait	80	Covered	T1,T3,T22
BootLoadIns->Error	188	Covered	T13,T44,T184
BootLoadIns->Idle	211	Covered	T185,T186,T187
BootLoadIns->RejectCsrngEntropy	188	Covered	T36,T188,T189
BootLoadUni->BootUniAckWait	107	Covered	T1,T22,T18
BootLoadUni->Error	188	Covered	T128,T190
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T191,T192,T193
BootPulse->BootDone	98	Covered	T1,T22,T18
BootPulse->Error	188	Covered	T194,T195
BootPulse->Idle	211	Covered	T95,T96,T196
BootPulse->RejectCsrngEntropy	188	Covered	T197,T198,T199
BootUniAckWait->Error	188	Not Covered
BootUniAckWait->Idle	112	Covered	T1,T22,T18
BootUniAckWait->RejectCsrngEntropy	188	Covered	T200,T201,T202
Idle->AutoLoadIns	69	Covered	T2,T3,T4
Idle->BootLoadIns	65	Covered	T1,T3,T22
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T3,T36,T93
Idle->SWPortMode	74	Covered	T1,T3,T7
RejectCsrngEntropy->Error	188	Covered	T203,T122,T204
RejectCsrngEntropy->Idle	211	Covered	T3,T18,T12
SWPortMode->Error	188	Covered	T205,T206,T207
SWPortMode->Idle	211	Covered	T5,T19,T20
SWPortMode->RejectCsrngEntropy	188	Covered	T18,T12,T35

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T18
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T18
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T18
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T18
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T22,T18
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T18,T13,T33
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T18
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T22,T23
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T22,T18
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T7,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T3,T4
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T7,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T7,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T11,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T7,T11,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T7,T11,T16
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T7,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T7,T11
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T7,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T7,T11
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T11,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T11,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T7,T11,T15
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T12
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T55,T56,T84

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T2,T4,T6
1	0	1	-	Not Covered
1	0	0	-	Covered	T3,T18,T12
0	-	-	1	Covered	T2,T3,T4
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	217704587	87902	0	0
FpvSecCmErrorStEscalate_A	217704587	88037	0	0
u_state_regs_A	217668841	217564711	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	87902	0	0
T2	1616	646	0	0
T3	2798	0	0	0
T4	1836	1062	0	0
T6	0	360	0	0
T7	5698	0	0	0
T13	0	768	0	0
T14	0	839	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	316	0	0
T42	0	802	0	0
T48	1813	0	0	0
T55	0	456	0	0
T56	0	850	0	0
T83	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	88037	0	0
T2	1616	647	0	0
T3	2798	0	0	0
T4	1836	1063	0	0
T6	0	361	0	0
T7	5698	0	0	0
T13	0	769	0	0
T14	0	840	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	317	0	0
T42	0	803	0	0
T48	1813	0	0	0
T55	0	457	0	0
T56	0	851	0	0
T83	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217668841	217564711	0	0
T1	2080	1988	0	0
T2	1328	1164	0	0
T3	2798	2731	0	0
T4	1710	1577	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0