Module Definition
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Module : prim_onehot_check
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 94.44

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check 94.44 94.44



Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 94.44


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 94.44


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_onehot_check
TotalCoveredPercent
Totals 5 4 80.00
Total Bits 36 34 94.44
Total Bits 0->1 18 17 94.44
Total Bits 1->0 18 17 94.44

Ports 5 4 80.00
Port Bits 36 34 94.44
Port Bits 0->1 18 17 94.44
Port Bits 1->0 18 17 94.44

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
oh_i[8:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
oh_i[10:9] Unreachable Unreachable Unreachable INPUT
oh_i[14:11] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
oh_i[15] Unreachable Unreachable Unreachable INPUT
oh_i[16] Yes Yes *T2,*T7,*T22 Yes T2,T7,T22 INPUT
oh_i[17] Unreachable Unreachable Unreachable INPUT
addr_i[4:0] Unreachable Unreachable Unreachable INPUT
en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
err_o No No No OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%