Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	95.71	100.00	100.00		78.57	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T7,T22
DataWait	75	Covered	T1,T2,T7
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T95,T96
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T7,T22
DataWait->AckPls	80	Covered	T1,T7,T22
DataWait->Disabled	107	Covered	T15,T97,T98
DataWait->Error	99	Covered	T2,T14,T99
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T100,T101,T102
EndPointClear->Error	99	Covered	T4,T13,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T7
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T2,T6,T14

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T7,T22
Idle	-	1	0	-	Covered	T1,T2,T7
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T7,T22
DataWait	-	-	-	0	Covered	T1,T2,T7
AckPls	-	-	-	-	Covered	T1,T7,T22
Error	-	-	-	-	Covered	T2,T4,T6
default	-	-	-	-	Covered	T2,T6,T83

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T6
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1523932109	625514	0	0
FpvSecCmErrorStEscalate_A	1523932109	626459	0	0
u_state_regs_A	1523896363	1523167453	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523932109	625514	0	0
T2	11312	4472	0	0
T3	19586	0	0	0
T4	12852	7434	0	0
T6	0	2470	0	0
T7	39886	0	0	0
T13	0	5376	0	0
T14	0	5873	0	0
T18	9772	0	0	0
T22	13923	0	0	0
T23	22078	0	0	0
T38	11592	0	0	0
T40	7490	0	0	0
T41	0	2212	0	0
T42	0	5614	0	0
T48	12691	0	0	0
T55	0	3542	0	0
T56	0	6300	0	0
T83	0	4080	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523932109	626459	0	0
T2	11312	4479	0	0
T3	19586	0	0	0
T4	12852	7441	0	0
T6	0	2477	0	0
T7	39886	0	0	0
T13	0	5383	0	0
T14	0	5880	0	0
T18	9772	0	0	0
T22	13923	0	0	0
T23	22078	0	0	0
T38	11592	0	0	0
T40	7490	0	0	0
T41	0	2219	0	0
T42	0	5621	0	0
T48	12691	0	0	0
T55	0	3549	0	0
T56	0	6307	0	0
T83	0	4087	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523896363	1523167453	0	0
T1	14560	13916	0	0
T2	11024	9876	0	0
T3	19586	19117	0	0
T4	12726	11795	0	0
T7	39886	39522	0	0
T18	9772	9366	0	0
T22	13923	13412	0	0
T23	22078	21567	0	0
T38	11592	11067	0	0
T40	7490	7119	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T24,T29
DataWait	75	Covered	T2,T23,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T24,T29
DataWait->AckPls	80	Covered	T23,T24,T29
DataWait->Disabled	107	Covered	T98,T103,T104
DataWait->Error	99	Covered	T2,T105,T106
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T100,T101,T102
EndPointClear->Error	99	Covered	T4,T13,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T23,T24
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T6,T14,T41

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T24,T29
Idle	-	1	0	-	Covered	T2,T23,T24
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T24,T29
DataWait	-	-	-	0	Covered	T2,T23,T24
AckPls	-	-	-	-	Covered	T23,T24,T29
Error	-	-	-	-	Covered	T2,T4,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T6
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217704587	89752	0	0
FpvSecCmErrorStEscalate_A	217704587	89887	0	0
u_state_regs_A	217704587	217600457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89752	0	0
T2	1616	646	0	0
T3	2798	0	0	0
T4	1836	1062	0	0
T6	0	360	0	0
T7	5698	0	0	0
T13	0	768	0	0
T14	0	839	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	316	0	0
T42	0	802	0	0
T48	1813	0	0	0
T55	0	506	0	0
T56	0	900	0	0
T83	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89887	0	0
T2	1616	647	0	0
T3	2798	0	0	0
T4	1836	1063	0	0
T6	0	361	0	0
T7	5698	0	0	0
T13	0	769	0	0
T14	0	840	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	317	0	0
T42	0	803	0	0
T48	1813	0	0	0
T55	0	507	0	0
T56	0	901	0	0
T83	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T7,T23
DataWait	75	Covered	T1,T7,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T7,T23
DataWait->AckPls	80	Covered	T1,T7,T23
DataWait->Disabled	107	Covered	T15,T107
DataWait->Error	99	Covered	T108,T109,T110
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T100,T101,T102
EndPointClear->Error	99	Covered	T4,T13,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T7,T23
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T2,T6,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T7,T23
Idle	-	1	0	-	Covered	T1,T7,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T7,T23
DataWait	-	-	-	0	Covered	T1,T7,T23
AckPls	-	-	-	-	Covered	T1,T7,T23
Error	-	-	-	-	Covered	T2,T4,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T6
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217704587	89752	0	0
FpvSecCmErrorStEscalate_A	217704587	89887	0	0
u_state_regs_A	217704587	217600457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89752	0	0
T2	1616	646	0	0
T3	2798	0	0	0
T4	1836	1062	0	0
T6	0	360	0	0
T7	5698	0	0	0
T13	0	768	0	0
T14	0	839	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	316	0	0
T42	0	802	0	0
T48	1813	0	0	0
T55	0	506	0	0
T56	0	900	0	0
T83	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89887	0	0
T2	1616	647	0	0
T3	2798	0	0	0
T4	1836	1063	0	0
T6	0	361	0	0
T7	5698	0	0	0
T13	0	769	0	0
T14	0	840	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	317	0	0
T42	0	803	0	0
T48	1813	0	0	0
T55	0	507	0	0
T56	0	901	0	0
T83	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T22,T23
DataWait	75	Covered	T3,T22,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T22,T23
DataWait->AckPls	80	Covered	T3,T22,T23
DataWait->Disabled	107	Covered	T111,T112,T113
DataWait->Error	99	Covered	T83,T114,T115
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T100,T101,T102
EndPointClear->Error	99	Covered	T4,T13,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T22,T23
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T2,T6,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T22,T23
Idle	-	1	0	-	Covered	T3,T22,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T22,T23
DataWait	-	-	-	0	Covered	T3,T22,T23
AckPls	-	-	-	-	Covered	T3,T22,T23
Error	-	-	-	-	Covered	T2,T4,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T6
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217704587	89752	0	0
FpvSecCmErrorStEscalate_A	217704587	89887	0	0
u_state_regs_A	217704587	217600457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89752	0	0
T2	1616	646	0	0
T3	2798	0	0	0
T4	1836	1062	0	0
T6	0	360	0	0
T7	5698	0	0	0
T13	0	768	0	0
T14	0	839	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	316	0	0
T42	0	802	0	0
T48	1813	0	0	0
T55	0	506	0	0
T56	0	900	0	0
T83	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89887	0	0
T2	1616	647	0	0
T3	2798	0	0	0
T4	1836	1063	0	0
T6	0	361	0	0
T7	5698	0	0	0
T13	0	769	0	0
T14	0	840	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	317	0	0
T42	0	803	0	0
T48	1813	0	0	0
T55	0	507	0	0
T56	0	901	0	0
T83	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T7,T23,T24
DataWait	75	Covered	T7,T23,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T96
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T7,T23,T24
DataWait->AckPls	80	Covered	T7,T23,T24
DataWait->Disabled	107	Covered	T116,T117,T118
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T100,T101,T102
EndPointClear->Error	99	Covered	T4,T13,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T7,T23,T24
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T2,T6,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T7,T23,T24
Idle	-	1	0	-	Covered	T7,T23,T24
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T7,T23,T24
DataWait	-	-	-	0	Covered	T7,T23,T24
AckPls	-	-	-	-	Covered	T7,T23,T24
Error	-	-	-	-	Covered	T2,T4,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T6
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217704587	89752	0	0
FpvSecCmErrorStEscalate_A	217704587	89887	0	0
u_state_regs_A	217704587	217600457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89752	0	0
T2	1616	646	0	0
T3	2798	0	0	0
T4	1836	1062	0	0
T6	0	360	0	0
T7	5698	0	0	0
T13	0	768	0	0
T14	0	839	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	316	0	0
T42	0	802	0	0
T48	1813	0	0	0
T55	0	506	0	0
T56	0	900	0	0
T83	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89887	0	0
T2	1616	647	0	0
T3	2798	0	0	0
T4	1836	1063	0	0
T6	0	361	0	0
T7	5698	0	0	0
T13	0	769	0	0
T14	0	840	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	317	0	0
T42	0	803	0	0
T48	1813	0	0	0
T55	0	507	0	0
T56	0	901	0	0
T83	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T24,T12
DataWait	75	Covered	T23,T24,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T24,T12
DataWait->AckPls	80	Covered	T23,T24,T12
DataWait->Disabled	107	Covered	T119
DataWait->Error	99	Covered	T120,T121,T122
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T100,T101,T102
EndPointClear->Error	99	Covered	T4,T13,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T24,T12
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T2,T6,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T24,T12
Idle	-	1	0	-	Covered	T23,T24,T12
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T24,T12
DataWait	-	-	-	0	Covered	T23,T24,T12
AckPls	-	-	-	-	Covered	T23,T24,T12
Error	-	-	-	-	Covered	T2,T4,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T6
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217704587	89752	0	0
FpvSecCmErrorStEscalate_A	217704587	89887	0	0
u_state_regs_A	217704587	217600457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89752	0	0
T2	1616	646	0	0
T3	2798	0	0	0
T4	1836	1062	0	0
T6	0	360	0	0
T7	5698	0	0	0
T13	0	768	0	0
T14	0	839	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	316	0	0
T42	0	802	0	0
T48	1813	0	0	0
T55	0	506	0	0
T56	0	900	0	0
T83	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89887	0	0
T2	1616	647	0	0
T3	2798	0	0	0
T4	1836	1063	0	0
T6	0	361	0	0
T7	5698	0	0	0
T13	0	769	0	0
T14	0	840	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	317	0	0
T42	0	803	0	0
T48	1813	0	0	0
T55	0	507	0	0
T56	0	901	0	0
T83	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T7,T22
DataWait	75	Covered	T1,T7,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T7,T22
DataWait->AckPls	80	Covered	T1,T7,T22
DataWait->Disabled	107	Covered	T97,T123,T124
DataWait->Error	99	Covered	T14,T99,T125
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T100,T101,T102
EndPointClear->Error	99	Covered	T4,T13,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T7,T22
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T41,T42,T56

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T7,T22
Idle	-	1	0	-	Covered	T1,T7,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T7,T22
DataWait	-	-	-	0	Covered	T1,T7,T22
AckPls	-	-	-	-	Covered	T1,T7,T22
Error	-	-	-	-	Covered	T2,T4,T6
default	-	-	-	-	Covered	T2,T6,T83

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T6
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217704587	87002	0	0
FpvSecCmErrorStEscalate_A	217704587	87137	0	0
u_state_regs_A	217668841	217564711	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	87002	0	0
T2	1616	596	0	0
T3	2798	0	0	0
T4	1836	1062	0	0
T6	0	310	0	0
T7	5698	0	0	0
T13	0	768	0	0
T14	0	839	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	316	0	0
T42	0	802	0	0
T48	1813	0	0	0
T55	0	506	0	0
T56	0	900	0	0
T83	0	540	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	87137	0	0
T2	1616	597	0	0
T3	2798	0	0	0
T4	1836	1063	0	0
T6	0	311	0	0
T7	5698	0	0	0
T13	0	769	0	0
T14	0	840	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	317	0	0
T42	0	803	0	0
T48	1813	0	0	0
T55	0	507	0	0
T56	0	901	0	0
T83	0	541	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217668841	217564711	0	0
T1	2080	1988	0	0
T2	1328	1164	0	0
T3	2798	2731	0	0
T4	1710	1577	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T7,T23,T25
DataWait	75	Covered	T7,T23,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T4,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T95
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T7,T23,T25
DataWait->AckPls	80	Covered	T7,T23,T25
DataWait->Disabled	107	Covered	T126,T127
DataWait->Error	99	Covered	T128,T129,T130
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T100,T101,T102
EndPointClear->Error	99	Covered	T4,T13,T55
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T7,T23,T25
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T2,T6,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T7,T23,T25
Idle	-	1	0	-	Covered	T7,T23,T25
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T7,T23,T25
DataWait	-	-	-	0	Covered	T7,T23,T25
AckPls	-	-	-	-	Covered	T7,T23,T25
Error	-	-	-	-	Covered	T2,T4,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T6
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217704587	89752	0	0
FpvSecCmErrorStEscalate_A	217704587	89887	0	0
u_state_regs_A	217704587	217600457	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89752	0	0
T2	1616	646	0	0
T3	2798	0	0	0
T4	1836	1062	0	0
T6	0	360	0	0
T7	5698	0	0	0
T13	0	768	0	0
T14	0	839	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	316	0	0
T42	0	802	0	0
T48	1813	0	0	0
T55	0	506	0	0
T56	0	900	0	0
T83	0	590	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	89887	0	0
T2	1616	647	0	0
T3	2798	0	0	0
T4	1836	1063	0	0
T6	0	361	0	0
T7	5698	0	0	0
T13	0	769	0	0
T14	0	840	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T41	0	317	0	0
T42	0	803	0	0
T48	1813	0	0	0
T55	0	507	0	0
T56	0	901	0	0
T83	0	591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0