Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.58	100.00	83.78	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T75,T77,T80
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T19,T74,T79
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	435055864	1010291	0	0
DepthKnown_A	435409174	435200914	0	0
RvalidKnown_A	435409174	435200914	0	0
WreadyKnown_A	435409174	435200914	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	435409174	1097561	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435055864	1010291	0	0
T2	504	171	0	0
T3	5596	627	0	0
T4	296	99	0	0
T6	0	77	0	0
T7	11396	8800	0	0
T11	0	1753	0	0
T12	0	1009	0	0
T14	0	120	0	0
T18	2792	0	0	0
T22	3978	0	0	0
T23	6308	0	0	0
T35	0	252	0	0
T38	3312	0	0	0
T40	2140	0	0	0
T48	3626	0	0	0
T55	0	289	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435409174	435200914	0	0
T1	4160	3976	0	0
T2	3232	2904	0	0
T3	5596	5462	0	0
T4	3672	3406	0	0
T7	11396	11292	0	0
T18	2792	2676	0	0
T22	3978	3832	0	0
T23	6308	6162	0	0
T38	3312	3162	0	0
T40	2140	2034	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435409174	435200914	0	0
T1	4160	3976	0	0
T2	3232	2904	0	0
T3	5596	5462	0	0
T4	3672	3406	0	0
T7	11396	11292	0	0
T18	2792	2676	0	0
T22	3978	3832	0	0
T23	6308	6162	0	0
T38	3312	3162	0	0
T40	2140	2034	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435409174	435200914	0	0
T1	4160	3976	0	0
T2	3232	2904	0	0
T3	5596	5462	0	0
T4	3672	3406	0	0
T7	11396	11292	0	0
T18	2792	2676	0	0
T22	3978	3832	0	0
T23	6308	6162	0	0
T38	3312	3162	0	0
T40	2140	2034	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	435409174	1097561	0	0
T2	3232	1270	0	0
T3	5596	627	0	0
T4	3672	1346	0	0
T6	0	670	0	0
T7	11396	8800	0	0
T11	0	1753	0	0
T12	0	1009	0	0
T13	0	264	0	0
T14	0	1453	0	0
T18	2792	0	0	0
T22	3978	0	0	0
T23	6308	0	0	0
T35	0	252	0	0
T38	3312	0	0	0
T40	2140	0	0	0
T48	3626	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T75,T77,T81
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	217527932	511133	0	0
DepthKnown_A	217704587	217600457	0	0
RvalidKnown_A	217704587	217600457	0	0
WreadyKnown_A	217704587	217600457	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	217704587	555138	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217527932	511133	0	0
T2	252	101	0	0
T3	2798	348	0	0
T4	148	54	0	0
T6	0	42	0	0
T7	5698	4406	0	0
T11	0	892	0	0
T12	0	522	0	0
T14	0	102	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T35	0	125	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T48	1813	0	0	0
T55	0	150	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	555138	0	0
T2	1616	589	0	0
T3	2798	348	0	0
T4	1836	688	0	0
T6	0	347	0	0
T7	5698	4406	0	0
T11	0	892	0	0
T12	0	522	0	0
T13	0	126	0	0
T14	0	776	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T35	0	125	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T48	1813	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T68,T82
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T80
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T19,T74,T79
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T7,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	217527932	499158	0	0
DepthKnown_A	217704587	217600457	0	0
RvalidKnown_A	217704587	217600457	0	0
WreadyKnown_A	217704587	217600457	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	217704587	542423	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217527932	499158	0	0
T2	252	70	0	0
T3	2798	279	0	0
T4	148	45	0	0
T6	0	35	0	0
T7	5698	4394	0	0
T11	0	861	0	0
T12	0	487	0	0
T14	0	18	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T35	0	127	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T48	1813	0	0	0
T55	0	139	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	542423	0	0
T2	1616	681	0	0
T3	2798	279	0	0
T4	1836	658	0	0
T6	0	323	0	0
T7	5698	4394	0	0
T11	0	861	0	0
T12	0	487	0	0
T13	0	138	0	0
T14	0	677	0	0
T18	1396	0	0	0
T22	1989	0	0	0
T23	3154	0	0	0
T35	0	127	0	0
T38	1656	0	0	0
T40	1070	0	0	0
T48	1813	0	0	0