Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.16	95.00	92.31			100.00	93.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb	95.16	95.00	92.31			100.00	93.33

---

Module Instance : tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.16	95.00	92.31			100.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.16	95.00	92.31			100.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
TOTAL		20	19	95.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
CONT_ASSIGN	120	1	0	0.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
120	0	1
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	217704587	217600457	0	0
CheckNGreaterZero_A	960	960	0	0
GntImpliesReady_A	217704587	23895	0	0
GntImpliesValid_A	217704587	23895	0	0
GrantKnown_A	217704587	217600457	0	0
IdxKnown_A	217704587	217600457	0	0
IndexIsCorrect_A	217704587	23895	0	0
LockArbDecision_A	217704587	588846	0	0
NoReadyValidNoGrant_A	217704587	216862167	0	0
ReadyAndValidImplyGrant_A	217704587	23895	0	0
ReqAndReadyImplyGrant_A	217704587	23895	0	0
ReqImpliesValid_A	217704587	612829	0	0
ReqStaysHighUntilGranted0_M	217704587	588846	0	0
RoundRobin_A	217704587	0	0	960
ValidKnown_A	217704587	217600457	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	960	960	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T38	1	1	0	0
T40	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	23895	0	0
T1	2080	32	0	0
T2	1616	1	0	0
T3	2798	2	0	0
T4	1836	0	0	0
T7	5698	241	0	0
T18	1396	2	0	0
T22	1989	25	0	0
T23	3154	42	0	0
T38	1656	0	0	0
T40	1070	1	0	0
T48	0	14	0	0
T49	0	1	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	23895	0	0
T1	2080	32	0	0
T2	1616	1	0	0
T3	2798	2	0	0
T4	1836	0	0	0
T7	5698	241	0	0
T18	1396	2	0	0
T22	1989	25	0	0
T23	3154	42	0	0
T38	1656	0	0	0
T40	1070	1	0	0
T48	0	14	0	0
T49	0	1	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	23895	0	0
T1	2080	32	0	0
T2	1616	1	0	0
T3	2798	2	0	0
T4	1836	0	0	0
T7	5698	241	0	0
T18	1396	2	0	0
T22	1989	25	0	0
T23	3154	42	0	0
T38	1656	0	0	0
T40	1070	1	0	0
T48	0	14	0	0
T49	0	1	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	588846	0	0
T1	2080	711	0	0
T2	1616	106	0	0
T3	2798	0	0	0
T4	1836	1063	0	0
T7	5698	1666	0	0
T18	1396	15	0	0
T22	1989	520	0	0
T23	3154	1543	0	0
T38	1656	0	0	0
T40	1070	45	0	0
T48	0	570	0	0
T49	0	31	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	216862167	0	0
T1	2080	1237	0	0
T2	1616	1345	0	0
T3	2798	2629	0	0
T4	1836	639	0	0
T7	5698	2944	0	0
T18	1396	1321	0	0
T22	1989	1366	0	0
T23	3154	1488	0	0
T38	1656	1581	0	0
T40	1070	971	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	23895	0	0
T1	2080	32	0	0
T2	1616	1	0	0
T3	2798	2	0	0
T4	1836	0	0	0
T7	5698	241	0	0
T18	1396	2	0	0
T22	1989	25	0	0
T23	3154	42	0	0
T38	1656	0	0	0
T40	1070	1	0	0
T48	0	14	0	0
T49	0	1	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	23895	0	0
T1	2080	32	0	0
T2	1616	1	0	0
T3	2798	2	0	0
T4	1836	0	0	0
T7	5698	241	0	0
T18	1396	2	0	0
T22	1989	25	0	0
T23	3154	42	0	0
T38	1656	0	0	0
T40	1070	1	0	0
T48	0	14	0	0
T49	0	1	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	612829	0	0
T1	2080	743	0	0
T2	1616	107	0	0
T3	2798	2	0	0
T4	1836	1064	0	0
T7	5698	1907	0	0
T18	1396	17	0	0
T22	1989	545	0	0
T23	3154	1585	0	0
T38	1656	0	0	0
T40	1070	46	0	0
T48	0	584	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	588846	0	0
T1	2080	711	0	0
T2	1616	106	0	0
T3	2798	0	0	0
T4	1836	1063	0	0
T7	5698	1666	0	0
T18	1396	15	0	0
T22	1989	520	0	0
T23	3154	1543	0	0
T38	1656	0	0	0
T40	1070	45	0	0
T48	0	570	0	0
T49	0	31	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	0	0	960

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217704587	217600457	0	0
T1	2080	1988	0	0
T2	1616	1452	0	0
T3	2798	2731	0	0
T4	1836	1703	0	0
T7	5698	5646	0	0
T18	1396	1338	0	0
T22	1989	1916	0	0
T23	3154	3081	0	0
T38	1656	1581	0	0
T40	1070	1017	0	0