Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	136	1			T25	1		T42	1		T69	1
auto_req_mode	142	1			T16	1		T8	1		T82	1
sw_mode	3072	1			T1	63		T44	1		T24	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

291

1

T42

1

T24

1

T69

1

single

109

1

T25

1

T40

1

T82

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1621	1			T44	1		T25	1		T42	1
auto[2]	202	1			T282	1		T301	1		T302	1
auto[3]	20	1			T76	1		T32	1		T303	1
auto[4]	121	1			T24	1		T304	1		T305	5
auto[5]	204	1			T8	1		T224	76		T306	1
auto[6]	63	1			T85	1		T30	1		T52	1
auto[7]	1119	1			T1	63		T40	1		T16	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	90	1			T25	1		T42	1		T69	1
auto[1]	auto_req_mode	91	1			T17	1		T248	1		T18	1
auto[1]	sw_mode	1440	1			T44	1		T81	1		T91	1
auto[2]	boot_req_mode	2	1			T301	1		T307	1		-	-
auto[2]	auto_req_mode	2	1			T308	1		T309	1		-	-
auto[2]	sw_mode	198	1			T282	1		T302	1		T310	24
auto[3]	boot_req_mode	3	1			T32	1		T311	1		T312	1
auto[3]	auto_req_mode	5	1			T303	1		T313	1		T314	1
auto[3]	sw_mode	12	1			T76	1		T315	1		T316	1
auto[4]	boot_req_mode	8	1			T317	1		T318	1		T319	1
auto[4]	auto_req_mode	3	1			T304	1		T320	1		T321	1
auto[4]	sw_mode	110	1			T24	1		T305	5		T322	1
auto[5]	boot_req_mode	3	1			T323	1		T324	1		T325	1
auto[5]	auto_req_mode	3	1			T8	1		T306	1		T326	1
auto[5]	sw_mode	198	1			T224	76		T327	42		T328	1
auto[6]	boot_req_mode	2	1			T329	1		T330	1		-	-
auto[6]	auto_req_mode	2	1			T30	1		T331	1		-	-
auto[6]	sw_mode	59	1			T85	1		T52	1		T332	38
auto[7]	boot_req_mode	28	1			T35	1		T36	1		T31	1
auto[7]	auto_req_mode	36	1			T16	1		T82	1		T37	1
auto[7]	sw_mode	1055	1			T1	63		T40	1		T23	1