Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	747250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6143836

1

T1

146807

T2

32

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1807942	1			T1	41289		T2	31		T3	34
values[0x0]	2349055	1			T1	56052		T2	13		T3	16
values[0x1]	2734089	1			T1	64952		T2	15		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	365513	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6525573

1

T1

155195

T2

40

T3

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26155	1			T1	637		T2	1		T3	5
valid_sources[0x01]	27296	1			T1	693		T3	1		T42	1
valid_sources[0x02]	26724	1			T1	637		T3	1		T19	1
valid_sources[0x03]	26469	1			T1	631		T15	1		T23	2
valid_sources[0x04]	26758	1			T1	607		T19	2		T28	1
valid_sources[0x05]	26904	1			T1	667		T40	1		T23	1
valid_sources[0x06]	27700	1			T1	579		T19	1		T28	1
valid_sources[0x07]	27011	1			T1	700		T42	1		T80	1
valid_sources[0x08]	27687	1			T1	593		T28	1		T5	1
valid_sources[0x09]	29006	1			T1	705		T40	1		T8	7
valid_sources[0x0a]	26729	1			T1	614		T11	1		T23	2
valid_sources[0x0b]	27606	1			T1	612		T79	2		T23	1
valid_sources[0x0c]	26792	1			T1	630		T8	3		T23	1
valid_sources[0x0d]	27870	1			T1	642		T40	1		T80	2
valid_sources[0x0e]	26120	1			T1	687		T3	1		T40	1
valid_sources[0x0f]	28433	1			T1	637		T15	1		T42	1
valid_sources[0x10]	26624	1			T1	662		T2	1		T25	1
valid_sources[0x11]	26434	1			T1	653		T3	1		T40	1
valid_sources[0x12]	27486	1			T1	679		T42	2		T11	2
valid_sources[0x13]	28223	1			T1	654		T23	2		T21	282
valid_sources[0x14]	25890	1			T1	607		T19	1		T40	2
valid_sources[0x15]	28063	1			T1	650		T2	2		T16	1
valid_sources[0x16]	26901	1			T1	621		T2	1		T44	2
valid_sources[0x17]	27421	1			T1	577		T19	1		T44	1
valid_sources[0x18]	27512	1			T1	632		T3	1		T11	1
valid_sources[0x19]	26502	1			T1	586		T28	2		T16	1
valid_sources[0x1a]	27977	1			T1	613		T15	1		T42	1
valid_sources[0x1b]	26781	1			T1	621		T11	2		T16	1
valid_sources[0x1c]	26758	1			T1	584		T19	1		T23	1
valid_sources[0x1d]	25176	1			T1	624		T14	2		T79	1
valid_sources[0x1e]	26442	1			T1	652		T23	1		T61	1
valid_sources[0x1f]	28807	1			T1	627		T42	1		T16	2
valid_sources[0x20]	25973	1			T1	631		T2	1		T19	1
valid_sources[0x21]	26336	1			T1	661		T2	1		T3	1
valid_sources[0x22]	26094	1			T1	588		T3	1		T19	3
valid_sources[0x23]	27051	1			T1	612		T19	1		T41	46
valid_sources[0x24]	26600	1			T1	665		T16	1		T23	2
valid_sources[0x25]	27136	1			T1	663		T3	2		T28	1
valid_sources[0x26]	26009	1			T1	666		T11	1		T8	1
valid_sources[0x27]	26372	1			T1	630		T19	2		T44	3
valid_sources[0x28]	27740	1			T1	614		T42	1		T23	3
valid_sources[0x29]	26503	1			T1	630		T14	1		T11	2
valid_sources[0x2a]	27465	1			T1	615		T3	1		T23	1
valid_sources[0x2b]	26456	1			T1	599		T42	1		T40	1
valid_sources[0x2c]	27635	1			T1	607		T5	1		T42	5
valid_sources[0x2d]	27169	1			T1	646		T16	1		T62	1
valid_sources[0x2e]	27613	1			T1	603		T16	2		T23	2
valid_sources[0x2f]	26616	1			T1	582		T2	1		T15	1
valid_sources[0x30]	27234	1			T1	604		T23	1		T83	1
valid_sources[0x31]	25286	1			T1	652		T14	1		T15	2
valid_sources[0x32]	28043	1			T1	666		T44	3		T42	3
valid_sources[0x33]	26250	1			T1	662		T2	2		T19	1
valid_sources[0x34]	26677	1			T1	666		T15	2		T8	3
valid_sources[0x35]	27606	1			T1	573		T28	3		T42	2
valid_sources[0x36]	26768	1			T1	656		T3	1		T5	1
valid_sources[0x37]	27714	1			T1	651		T2	1		T19	1
valid_sources[0x38]	25202	1			T1	598		T28	1		T14	2
valid_sources[0x39]	27632	1			T1	672		T28	1		T15	1
valid_sources[0x3a]	26388	1			T1	623		T19	1		T44	2
valid_sources[0x3b]	27209	1			T1	627		T19	1		T5	1
valid_sources[0x3c]	27588	1			T1	637		T3	1		T42	2
valid_sources[0x3d]	25904	1			T1	659		T2	1		T16	1
valid_sources[0x3e]	25018	1			T1	594		T44	2		T28	1
valid_sources[0x3f]	26332	1			T1	613		T80	1		T8	1
valid_sources[0x40]	27591	1			T1	598		T14	1		T42	1
valid_sources[0x41]	29248	1			T1	635		T16	1		T80	5
valid_sources[0x42]	26515	1			T1	690		T2	1		T14	4
valid_sources[0x43]	26870	1			T1	617		T42	1		T16	1
valid_sources[0x44]	27023	1			T1	630		T16	1		T23	1
valid_sources[0x45]	25231	1			T1	655		T79	2		T8	1
valid_sources[0x46]	26181	1			T1	629		T16	1		T23	1
valid_sources[0x47]	26110	1			T1	637		T44	2		T15	1
valid_sources[0x48]	24795	1			T1	667		T42	1		T80	4
valid_sources[0x49]	28711	1			T1	605		T40	1		T23	1
valid_sources[0x4a]	25258	1			T1	593		T19	1		T79	1
valid_sources[0x4b]	26966	1			T1	592		T28	1		T14	1
valid_sources[0x4c]	25780	1			T1	667		T19	2		T16	1
valid_sources[0x4d]	27125	1			T1	640		T23	1		T110	1
valid_sources[0x4e]	28782	1			T1	627		T19	3		T4	77
valid_sources[0x4f]	26883	1			T1	661		T15	1		T42	1
valid_sources[0x50]	25081	1			T1	602		T28	1		T16	2
valid_sources[0x51]	27284	1			T1	677		T14	1		T15	1
valid_sources[0x52]	27222	1			T1	613		T19	5		T11	1
valid_sources[0x53]	27343	1			T1	609		T3	1		T19	1
valid_sources[0x54]	26694	1			T1	663		T3	1		T21	211
valid_sources[0x55]	27746	1			T1	671		T15	1		T11	1
valid_sources[0x56]	28041	1			T1	627		T2	1		T28	1
valid_sources[0x57]	25343	1			T1	645		T3	1		T28	1
valid_sources[0x58]	28466	1			T1	608		T19	1		T15	1
valid_sources[0x59]	24812	1			T1	666		T16	1		T29	2
valid_sources[0x5a]	26626	1			T1	621		T2	1		T42	1
valid_sources[0x5b]	27572	1			T1	637		T5	1		T16	2
valid_sources[0x5c]	26845	1			T1	616		T2	1		T40	1
valid_sources[0x5d]	26904	1			T1	612		T2	1		T28	1
valid_sources[0x5e]	27100	1			T1	645		T19	3		T44	2
valid_sources[0x5f]	25480	1			T1	626		T2	1		T42	1
valid_sources[0x60]	28300	1			T1	697		T16	1		T110	1
valid_sources[0x61]	26411	1			T1	614		T40	1		T16	1
valid_sources[0x62]	26327	1			T1	617		T42	1		T40	1
valid_sources[0x63]	27504	1			T1	643		T2	1		T16	1
valid_sources[0x64]	26892	1			T1	602		T28	1		T79	2
valid_sources[0x65]	25141	1			T1	613		T2	1		T3	1
valid_sources[0x66]	28407	1			T1	658		T2	1		T3	1
valid_sources[0x67]	26231	1			T1	583		T28	1		T15	2
valid_sources[0x68]	27941	1			T1	646		T3	1		T16	1
valid_sources[0x69]	28206	1			T1	609		T3	1		T42	1
valid_sources[0x6a]	27513	1			T1	628		T28	1		T23	1
valid_sources[0x6b]	25448	1			T1	659		T3	2		T16	1
valid_sources[0x6c]	25967	1			T1	629		T14	39		T42	1
valid_sources[0x6d]	26211	1			T1	582		T42	2		T40	1
valid_sources[0x6e]	25911	1			T1	612		T2	1		T28	1
valid_sources[0x6f]	25810	1			T1	591		T42	1		T23	1
valid_sources[0x70]	28040	1			T1	648		T2	1		T23	1
valid_sources[0x71]	25074	1			T1	586		T42	1		T40	3
valid_sources[0x72]	28014	1			T1	666		T80	6		T23	3
valid_sources[0x73]	25876	1			T1	672		T2	1		T14	1
valid_sources[0x74]	27624	1			T1	611		T40	2		T16	1
valid_sources[0x75]	27144	1			T1	607		T42	1		T11	5
valid_sources[0x76]	28247	1			T1	659		T3	1		T28	1
valid_sources[0x77]	27176	1			T1	658		T42	1		T110	1
valid_sources[0x78]	26092	1			T1	604		T21	282		T281	1
valid_sources[0x79]	26178	1			T1	635		T2	9		T42	1
valid_sources[0x7a]	27750	1			T1	652		T2	1		T14	1
valid_sources[0x7b]	25671	1			T1	644		T42	1		T16	1
valid_sources[0x7c]	26071	1			T1	680		T3	2		T28	1
valid_sources[0x7d]	25725	1			T1	617		T15	1		T40	1
valid_sources[0x7e]	25666	1			T1	660		T5	1		T11	1
valid_sources[0x7f]	26433	1			T1	562		T41	7		T5	1
valid_sources[0x80]	26878	1			T1	660		T28	1		T42	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1545251

1

T1

37295

T2

13

T3

8

values[0x0]

all_enables

biggest_size

2300742

1

T1

55038

T2

13

T3

13

values[0x1]

all_enables

biggest_size

2297843

1

T1

54474

T2

6

T3

3