Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2954	1			T1	39		T24	2		T40	3
non_zero_bins[1]	2032	1			T1	33		T42	2		T16	3
zero	9770	1			T1	155		T2	9		T3	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	597	1			T1	7		T42	1		T24	1
uni	3912	1			T1	73		T2	1		T19	1
gen	4720	1			T1	63		T2	4		T3	3
res	873	1			T1	11		T2	1		T40	1
ins	4654	1			T1	73		T2	3		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9712

1

T1

161

T2

6

T3

2

mubi_true

5044

1

T1

66

T2

3

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

25

1

T11

1

T153

1

T277

1

pass

14731

1

T1

227

T2

9

T3

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	124	1			T1	1		T84	1		T278	1
upd	non_zero_bins[0]	pass	mubi_true	159	1			T1	1		T24	1		T80	1
upd	non_zero_bins[1]	pass	mubi_false	97	1			T1	3		T42	1		T32	1
upd	non_zero_bins[1]	pass	mubi_true	95	1			T1	1		T55	1		T222	1
upd	zero	pass	mubi_false	64	1			T1	1		T247	1		T21	1
upd	zero	pass	mubi_true	58	1			T23	1		T279	1		T280	2
uni	zero	pass	mubi_false	2896	1			T1	49		T2	1		T19	1
uni	zero	pass	mubi_true	1016	1			T1	24		T44	1		T81	1
gen	non_zero_bins[0]	pass	mubi_false	529	1			T1	6		T40	1		T91	1
gen	non_zero_bins[0]	pass	mubi_true	578	1			T1	8		T24	1		T16	3
gen	non_zero_bins[1]	pass	mubi_false	409	1			T1	9		T42	1		T17	3
gen	non_zero_bins[1]	pass	mubi_true	380	1			T1	2		T16	1		T247	1
gen	zero	fail	mubi_false	23	1			T11	1		T277	1		T249	1
gen	zero	pass	mubi_false	2080	1			T1	36		T2	2		T3	1
gen	zero	pass	mubi_true	721	1			T1	2		T2	2		T3	2
res	non_zero_bins[0]	pass	mubi_false	194	1			T1	2		T40	1		T82	2
res	non_zero_bins[0]	pass	mubi_true	201	1			T1	2		T248	2		T21	5
res	non_zero_bins[1]	pass	mubi_false	129	1			T1	1		T16	2		T17	2
res	non_zero_bins[1]	pass	mubi_true	167	1			T1	5		T91	1		T21	1
res	zero	fail	mubi_false	2	1			T153	1		T154	1		-	-
res	zero	pass	mubi_false	97	1			T2	1		T92	1		T281	2
res	zero	pass	mubi_true	83	1			T1	1		T8	2		T21	1
ins	non_zero_bins[0]	pass	mubi_false	596	1			T1	10		T16	1		T82	1
ins	non_zero_bins[0]	pass	mubi_true	573	1			T1	9		T40	1		T80	1
ins	non_zero_bins[1]	pass	mubi_false	368	1			T1	5		T8	1		T21	6
ins	non_zero_bins[1]	pass	mubi_true	387	1			T1	7		T17	1		T27	1
ins	zero	pass	mubi_false	2104	1			T1	38		T2	2		T3	1
ins	zero	pass	mubi_true	626	1			T1	4		T2	1		T3	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded