Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	94.44		93.24	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.06	100.00	94.44		93.24	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	94.44		93.24	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.08	100.00	94.44		93.24	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T69,T11
1	1	Covered	T2,T19,T28

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T92
1	1	Covered	T2,T3,T4

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T19
1	0	Covered	T4,T20,T6

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T4,T20,T6

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T19
1	Covered	T4,T20,T6

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	69	93.24
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T3,T11
AutoCaptGenCnt	143	Covered	T2,T3,T4
AutoCaptReseedCnt	141	Covered	T2,T16,T8
AutoDispatch	125	Covered	T2,T3,T4
AutoFirstAckWait	119	Covered	T2,T3,T4
AutoLoadIns	69	Covered	T2,T3,T4
AutoSendGenCmd	150	Covered	T2,T3,T11
AutoSendReseedCmd	162	Covered	T2,T16,T8
BootDone	98	Covered	T2,T19,T28
BootGenAckWait	90	Covered	T2,T19,T28
BootInsAckWait	80	Covered	T2,T19,T28
BootLoadGen	85	Covered	T2,T19,T28
BootLoadIns	65	Covered	T2,T19,T28
BootLoadUni	102	Covered	T2,T19,T28
BootPulse	94	Covered	T2,T19,T28
BootUniAckWait	107	Covered	T2,T19,T28
Error	188	Covered	T4,T20,T6
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T2,T3,T19
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T2,T16,T8
AutoAckWait->Error	188	Covered	T57,T120,T121
AutoAckWait->Idle	211	Covered	T64,T67,T68
AutoAckWait->RejectCsrngEntropy	188	Covered	T2,T3,T11
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T3,T11
AutoCaptGenCnt->Error	188	Covered	T4,T122,T123
AutoCaptGenCnt->Idle	211	Covered	T124,T125,T126
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T77,T127,T128
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T2,T16,T8
AutoCaptReseedCnt->Error	188	Covered	T129,T130,T131
AutoCaptReseedCnt->Idle	211	Covered	T132,T133,T134
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T135,T114,T136
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T3,T4
AutoDispatch->AutoCaptReseedCnt	141	Covered	T2,T16,T8
AutoDispatch->Error	188	Covered	T137
AutoDispatch->Idle	138	Covered	T16,T8,T82
AutoDispatch->RejectCsrngEntropy	188	Covered	T87,T138,T139
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T3,T4
AutoFirstAckWait->Error	188	Not Covered
AutoFirstAckWait->Idle	211	Covered	T59,T140,T141
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T14,T118,T142
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T3,T4
AutoLoadIns->Error	188	Covered	T7,T12,T45
AutoLoadIns->Idle	211	Covered	T4,T14,T15
AutoLoadIns->RejectCsrngEntropy	188	Covered	T86,T143,T144
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T3,T11
AutoSendGenCmd->Error	188	Covered	T145
AutoSendGenCmd->Idle	211	Covered	T146,T147,T148
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T149,T116,T150
AutoSendReseedCmd->AutoAckWait	168	Covered	T2,T16,T8
AutoSendReseedCmd->Error	188	Not Covered
AutoSendReseedCmd->Idle	211	Covered	T111,T151,T152
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T153,T154,T115
BootDone->BootLoadUni	102	Covered	T2,T19,T28
BootDone->Error	188	Covered	T155,T60,T156
BootDone->Idle	211	Covered	T157,T158,T159
BootDone->RejectCsrngEntropy	188	Covered	T26,T160,T161
BootGenAckWait->BootPulse	94	Covered	T2,T19,T28
BootGenAckWait->Error	188	Covered	T162
BootGenAckWait->Idle	211	Covered	T69,T73,T163
BootGenAckWait->RejectCsrngEntropy	188	Covered	T41,T79,T164
BootInsAckWait->BootLoadGen	85	Covered	T2,T19,T28
BootInsAckWait->Error	188	Covered	T49,T50,T165
BootInsAckWait->Idle	211	Covered	T25,T70,T107
BootInsAckWait->RejectCsrngEntropy	188	Covered	T19,T15,T83
BootLoadGen->BootGenAckWait	90	Covered	T2,T19,T28
BootLoadGen->Error	188	Covered	T166,T48,T167
BootLoadGen->Idle	211	Covered	T168,T169,T170
BootLoadGen->RejectCsrngEntropy	188	Covered	T171,T172,T173
BootLoadIns->BootInsAckWait	80	Covered	T2,T19,T28
BootLoadIns->Error	188	Covered	T70,T174,T175
BootLoadIns->Idle	211	Covered	T176,T177,T178
BootLoadIns->RejectCsrngEntropy	188	Covered	T179,T180,T181
BootLoadUni->BootUniAckWait	107	Covered	T2,T19,T28
BootLoadUni->Error	188	Not Covered
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T182,T183,T184
BootPulse->BootDone	98	Covered	T2,T19,T28
BootPulse->Error	188	Covered	T185,T186,T187
BootPulse->Idle	211	Covered	T88,T34,T188
BootPulse->RejectCsrngEntropy	188	Covered	T28,T189
BootUniAckWait->Error	188	Covered	T13,T190
BootUniAckWait->Idle	112	Covered	T2,T19,T28
BootUniAckWait->RejectCsrngEntropy	188	Covered	T119,T191,T192
Idle->AutoLoadIns	69	Covered	T2,T3,T4
Idle->BootLoadIns	65	Covered	T2,T19,T28
Idle->Error	188	Not Covered
Idle->RejectCsrngEntropy	188	Covered	T28,T15,T79
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T193,T194,T195
RejectCsrngEntropy->Idle	211	Covered	T2,T3,T19
SWPortMode->Error	188	Covered	T72,T74,T196
SWPortMode->Idle	211	Covered	T1,T3,T41
SWPortMode->RejectCsrngEntropy	188	Covered	T2,T3,T19

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T28
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T28
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T28
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T28
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T28
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T28
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T28
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T28
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T19,T28
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T19,T28
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T19,T28
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T42,T80,T26
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T19,T28
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T3,T4
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T3,T4
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T3,T4
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T3,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T3,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T16,T8,T82
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T16,T8
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T3,T4
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T11,T16
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T8
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T16,T8
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T16,T8
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T19
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T6,T71

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T20,T6
1	0	1	-	Not Covered
1	0	0	-	Covered	T2,T3,T19
0	-	-	1	Covered	T2,T3,T19
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	244663004	77613	0	0
FpvSecCmErrorStEscalate_A	244663004	77744	0	0
u_state_regs_A	244629745	244526353	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	77613	0	0
T4	2344	1107	0	0
T5	1279	0	0	0
T6	0	710	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1058	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	350	0	0
T71	0	1090	0	0
T72	0	597	0	0
T73	0	506	0	0
T74	0	358	0	0
T107	0	1020	0	0
T196	0	398	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	77744	0	0
T4	2344	1108	0	0
T5	1279	0	0	0
T6	0	711	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1059	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	351	0	0
T71	0	1091	0	0
T72	0	598	0	0
T73	0	507	0	0
T74	0	359	0	0
T107	0	1021	0	0
T196	0	399	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244629745	244526353	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2042	1904	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0