Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	94.46	100.00	100.00		78.57	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	95.89	100.00	100.00		85.71	93.75	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.46	100.00	100.00		78.57	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	100.00		78.57	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	100.00	100.00		85.71	93.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	100.00	100.00		85.71	94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T20,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T34,T197,T198
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T25,T199,T200
DataWait->Error	99	Covered	T6,T107,T54
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T67,T68,T112
EndPointClear->Error	99	Covered	T70,T73,T7
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T20,T6

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T20,T6
default	-	-	-	-	Covered	T4,T70,T72

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T20,T6
0	1	Covered	T2,T3,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1712641028	559341	0	0
FpvSecCmErrorStEscalate_A	1712641028	560258	0	0
u_state_regs_A	1712607769	1711884025	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712641028	559341	0	0
T4	16408	7699	0	0
T5	8953	0	0	0
T6	0	5320	0	0
T14	18564	0	0	0
T15	14700	0	0	0
T20	0	7756	0	0
T24	7455	0	0	0
T25	7378	0	0	0
T28	17556	0	0	0
T41	18410	0	0	0
T42	9716	0	0	0
T44	10080	0	0	0
T70	0	2400	0	0
T71	0	7980	0	0
T72	0	4129	0	0
T73	0	3892	0	0
T74	0	2456	0	0
T107	0	7490	0	0
T196	0	2736	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712641028	560258	0	0
T4	16408	7706	0	0
T5	8953	0	0	0
T6	0	5327	0	0
T14	18564	0	0	0
T15	14700	0	0	0
T20	0	7763	0	0
T24	7455	0	0	0
T25	7378	0	0	0
T28	17556	0	0	0
T41	18410	0	0	0
T42	9716	0	0	0
T44	10080	0	0	0
T70	0	2407	0	0
T71	0	7987	0	0
T72	0	4136	0	0
T73	0	3899	0	0
T74	0	2463	0	0
T107	0	7497	0	0
T196	0	2743	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1712607769	1711884025	0	0
T1	5604165	5604060	0	0
T2	15596	15155	0	0
T3	12831	12390	0	0
T4	16106	15140	0	0
T14	18564	17976	0	0
T19	13601	12908	0	0
T25	7378	6748	0	0
T28	17556	17108	0	0
T41	18410	17864	0	0
T44	10080	9611	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T16,T8,T23
DataWait	75	Covered	T16,T8,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T20,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T16,T8,T23
DataWait->AckPls	80	Covered	T16,T8,T23
DataWait->Disabled	107	Covered	T201
DataWait->Error	99	Covered	T202,T195,T203
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T67,T68,T112
EndPointClear->Error	99	Covered	T70,T73,T7
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T16,T8,T23
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T20,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T16,T8,T23
Idle	-	1	0	-	Covered	T16,T8,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T16,T8,T23
DataWait	-	-	-	0	Covered	T16,T8,T23
AckPls	-	-	-	-	Covered	T16,T8,T23
Error	-	-	-	-	Covered	T4,T20,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T20,T6
0	1	Covered	T2,T3,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244663004	80213	0	0
FpvSecCmErrorStEscalate_A	244663004	80344	0	0
u_state_regs_A	244663004	244559612	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80213	0	0
T4	2344	1107	0	0
T5	1279	0	0	0
T6	0	760	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1108	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	350	0	0
T71	0	1140	0	0
T72	0	597	0	0
T73	0	556	0	0
T74	0	358	0	0
T107	0	1070	0	0
T196	0	398	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80344	0	0
T4	2344	1108	0	0
T5	1279	0	0	0
T6	0	761	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1109	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	351	0	0
T71	0	1141	0	0
T72	0	598	0	0
T73	0	557	0	0
T74	0	359	0	0
T107	0	1071	0	0
T196	0	399	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T14,T8
DataWait	75	Covered	T3,T14,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T20,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T14,T8
DataWait->AckPls	80	Covered	T3,T14,T8
DataWait->Disabled	107	Covered	T163,T204,T205
DataWait->Error	99	Covered	T6,T187,T206
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T67,T68,T112
EndPointClear->Error	99	Covered	T70,T73,T7
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T14,T8
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T20,T71

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T14,T8
Idle	-	1	0	-	Covered	T3,T14,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T14,T8
DataWait	-	-	-	0	Covered	T3,T14,T8
AckPls	-	-	-	-	Covered	T3,T14,T8
Error	-	-	-	-	Covered	T4,T20,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T20,T6
0	1	Covered	T2,T3,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244663004	80213	0	0
FpvSecCmErrorStEscalate_A	244663004	80344	0	0
u_state_regs_A	244663004	244559612	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80213	0	0
T4	2344	1107	0	0
T5	1279	0	0	0
T6	0	760	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1108	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	350	0	0
T71	0	1140	0	0
T72	0	597	0	0
T73	0	556	0	0
T74	0	358	0	0
T107	0	1070	0	0
T196	0	398	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80344	0	0
T4	2344	1108	0	0
T5	1279	0	0	0
T6	0	761	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1109	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	351	0	0
T71	0	1141	0	0
T72	0	598	0	0
T73	0	557	0	0
T74	0	359	0	0
T107	0	1071	0	0
T196	0	399	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T26,T27
DataWait	75	Covered	T23,T26,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T20,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T26,T27
DataWait->AckPls	80	Covered	T23,T26,T27
DataWait->Disabled	107	Covered	T124,T146,T207
DataWait->Error	99	Covered	T155,T60,T120
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T67,T68,T112
EndPointClear->Error	99	Covered	T70,T73,T7
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T26,T27
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T20,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T26,T27
Idle	-	1	0	-	Covered	T23,T26,T27
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T26,T27
DataWait	-	-	-	0	Covered	T23,T27,T88
AckPls	-	-	-	-	Covered	T23,T26,T27
Error	-	-	-	-	Covered	T4,T20,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T20,T6
0	1	Covered	T2,T3,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244663004	80213	0	0
FpvSecCmErrorStEscalate_A	244663004	80344	0	0
u_state_regs_A	244663004	244559612	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80213	0	0
T4	2344	1107	0	0
T5	1279	0	0	0
T6	0	760	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1108	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	350	0	0
T71	0	1140	0	0
T72	0	597	0	0
T73	0	556	0	0
T74	0	358	0	0
T107	0	1070	0	0
T196	0	398	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80344	0	0
T4	2344	1108	0	0
T5	1279	0	0	0
T6	0	761	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1109	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	351	0	0
T71	0	1141	0	0
T72	0	598	0	0
T73	0	557	0	0
T74	0	359	0	0
T107	0	1071	0	0
T196	0	399	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T8,T23
DataWait	75	Covered	T24,T8,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T20,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T34
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T8,T23
DataWait->AckPls	80	Covered	T24,T8,T23
DataWait->Disabled	107	Covered	T199,T200,T208
DataWait->Error	99	Covered	T145,T122
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T67,T68,T112
EndPointClear->Error	99	Covered	T70,T73,T7
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T24,T8,T23
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T20,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T24,T8,T23
Idle	-	1	0	-	Covered	T24,T8,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T24,T8,T23
DataWait	-	-	-	0	Covered	T24,T8,T23
AckPls	-	-	-	-	Covered	T24,T8,T23
Error	-	-	-	-	Covered	T4,T20,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T20,T6
0	1	Covered	T2,T3,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244663004	80213	0	0
FpvSecCmErrorStEscalate_A	244663004	80344	0	0
u_state_regs_A	244663004	244559612	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80213	0	0
T4	2344	1107	0	0
T5	1279	0	0	0
T6	0	760	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1108	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	350	0	0
T71	0	1140	0	0
T72	0	597	0	0
T73	0	556	0	0
T74	0	358	0	0
T107	0	1070	0	0
T196	0	398	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80344	0	0
T4	2344	1108	0	0
T5	1279	0	0	0
T6	0	761	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1109	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	351	0	0
T71	0	1141	0	0
T72	0	598	0	0
T73	0	557	0	0
T74	0	359	0	0
T107	0	1071	0	0
T196	0	399	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T16,T8
DataWait	75	Covered	T25,T16,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T20,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T209
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T16,T8
DataWait->AckPls	80	Covered	T25,T16,T8
DataWait->Disabled	107	Covered	T25,T169,T126
DataWait->Error	99	Covered	T166,T210,T121
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T67,T68,T112
EndPointClear->Error	99	Covered	T70,T73,T7
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T16,T8
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T20,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T16,T8
Idle	-	1	0	-	Covered	T25,T16,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T16,T8
DataWait	-	-	-	0	Covered	T25,T16,T8
AckPls	-	-	-	-	Covered	T25,T16,T8
Error	-	-	-	-	Covered	T4,T20,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T20,T6
0	1	Covered	T2,T3,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244663004	80213	0	0
FpvSecCmErrorStEscalate_A	244663004	80344	0	0
u_state_regs_A	244663004	244559612	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80213	0	0
T4	2344	1107	0	0
T5	1279	0	0	0
T6	0	760	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1108	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	350	0	0
T71	0	1140	0	0
T72	0	597	0	0
T73	0	556	0	0
T74	0	358	0	0
T107	0	1070	0	0
T196	0	398	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80344	0	0
T4	2344	1108	0	0
T5	1279	0	0	0
T6	0	761	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1109	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	351	0	0
T71	0	1141	0	0
T72	0	598	0	0
T73	0	557	0	0
T74	0	359	0	0
T107	0	1071	0	0
T196	0	399	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T16,T23,T27
DataWait	75	Covered	T4,T16,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T20,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T197,T211
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T16,T23,T27
DataWait->AckPls	80	Covered	T16,T23,T27
DataWait->Disabled	107	Covered	T168,T170
DataWait->Error	99	Covered	T4,T212,T213
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T67,T68,T112
EndPointClear->Error	99	Covered	T70,T73,T7
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T4,T16,T23
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T20,T6,T71

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	15	93.75
IF	52	2	2	100.00
CASE	60	11	10	90.91
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T16,T23,T27
Idle	-	1	0	-	Covered	T4,T16,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T16,T23,T27
DataWait	-	-	-	0	Covered	T4,T16,T23
AckPls	-	-	-	-	Covered	T16,T23,T27
Error	-	-	-	-	Covered	T4,T20,T6
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T20,T6
0	1	Covered	T2,T3,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244663004	80213	0	0
FpvSecCmErrorStEscalate_A	244663004	80344	0	0
u_state_regs_A	244663004	244559612	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80213	0	0
T4	2344	1107	0	0
T5	1279	0	0	0
T6	0	760	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1108	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	350	0	0
T71	0	1140	0	0
T72	0	597	0	0
T73	0	556	0	0
T74	0	358	0	0
T107	0	1070	0	0
T196	0	398	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	80344	0	0
T4	2344	1108	0	0
T5	1279	0	0	0
T6	0	761	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1109	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	351	0	0
T71	0	1141	0	0
T72	0	598	0	0
T73	0	557	0	0
T74	0	359	0	0
T107	0	1071	0	0
T196	0	399	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T19
DataWait	75	Covered	T1,T2,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T20,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T198
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T19
DataWait->AckPls	80	Covered	T1,T2,T19
DataWait->Disabled	107	Covered	T147,T214,T215
DataWait->Error	99	Covered	T107,T54,T216
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Not Covered
EndPointClear->Disabled	107	Covered	T67,T68,T112
EndPointClear->Error	99	Covered	T73,T7,T12
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T19
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T20,T6,T71

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T19
Idle	-	1	0	-	Covered	T1,T2,T19
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T19
DataWait	-	-	-	0	Covered	T1,T2,T19
AckPls	-	-	-	-	Covered	T1,T2,T19
Error	-	-	-	-	Covered	T4,T20,T6
default	-	-	-	-	Covered	T4,T70,T72

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T20,T6
0	1	Covered	T2,T3,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244663004	78063	0	0
FpvSecCmErrorStEscalate_A	244663004	78194	0	0
u_state_regs_A	244629745	244526353	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	78063	0	0
T4	2344	1057	0	0
T5	1279	0	0	0
T6	0	760	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1108	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	300	0	0
T71	0	1140	0	0
T72	0	547	0	0
T73	0	556	0	0
T74	0	308	0	0
T107	0	1070	0	0
T196	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	78194	0	0
T4	2344	1058	0	0
T5	1279	0	0	0
T6	0	761	0	0
T14	2652	0	0	0
T15	2100	0	0	0
T20	0	1109	0	0
T24	1065	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T42	1388	0	0	0
T44	1440	0	0	0
T70	0	301	0	0
T71	0	1141	0	0
T72	0	548	0	0
T73	0	557	0	0
T74	0	309	0	0
T107	0	1071	0	0
T196	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244629745	244526353	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2042	1904	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0