Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.58	100.00	83.78	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	100.00	86.49	94.12		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.06	100.00	90.00			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	96.36	100.00	91.30	94.12		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T100,T102
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T75,T96,T97
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488997776	1027506	0	0
DepthKnown_A	489326008	489119224	0	0
RvalidKnown_A	489326008	489119224	0	0
WreadyKnown_A	489326008	489119224	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	489326008	1100574	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488997776	1027506	0	0
T2	4456	556	0	0
T3	3666	379	0	0
T4	566	271	0	0
T5	700	0	0	0
T8	0	2567	0	0
T11	0	387	0	0
T14	5304	995	0	0
T15	0	443	0	0
T16	0	11071	0	0
T19	3886	0	0	0
T25	2108	0	0	0
T28	5016	0	0	0
T41	5260	0	0	0
T44	2880	0	0	0
T79	0	208	0	0
T82	0	1153	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489326008	489119224	0	0
T1	1601190	1601160	0	0
T2	4456	4330	0	0
T3	3666	3540	0	0
T4	4688	4412	0	0
T14	5304	5136	0	0
T19	3886	3688	0	0
T25	2108	1928	0	0
T28	5016	4888	0	0
T41	5260	5104	0	0
T44	2880	2746	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489326008	489119224	0	0
T1	1601190	1601160	0	0
T2	4456	4330	0	0
T3	3666	3540	0	0
T4	4688	4412	0	0
T14	5304	5136	0	0
T19	3886	3688	0	0
T25	2108	1928	0	0
T28	5016	4888	0	0
T41	5260	5104	0	0
T44	2880	2746	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489326008	489119224	0	0
T1	1601190	1601160	0	0
T2	4456	4330	0	0
T3	3666	3540	0	0
T4	4688	4412	0	0
T14	5304	5136	0	0
T19	3886	3688	0	0
T25	2108	1928	0	0
T28	5016	4888	0	0
T41	5260	5104	0	0
T44	2880	2746	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	489326008	1100574	0	0
T2	4456	556	0	0
T3	3666	379	0	0
T4	4688	1968	0	0
T5	2558	0	0	0
T8	0	2567	0	0
T11	0	387	0	0
T14	5304	995	0	0
T15	0	443	0	0
T16	0	11071	0	0
T19	3886	0	0	0
T25	2108	0	0	0
T28	5016	0	0	0
T41	5260	0	0	0
T44	2880	0	0	0
T79	0	208	0	0
T82	0	1153	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T75,T103
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	244498888	519381	0	0
DepthKnown_A	244663004	244559612	0	0
RvalidKnown_A	244663004	244559612	0	0
WreadyKnown_A	244663004	244559612	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	244663004	555969	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244498888	519381	0	0
T2	2228	273	0	0
T3	1833	188	0	0
T4	283	157	0	0
T5	350	0	0	0
T8	0	1337	0	0
T11	0	192	0	0
T14	2652	541	0	0
T15	0	257	0	0
T16	0	5553	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T79	0	170	0	0
T82	0	608	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	555969	0	0
T2	2228	273	0	0
T3	1833	188	0	0
T4	2344	1010	0	0
T5	1279	0	0	0
T8	0	1337	0	0
T11	0	192	0	0
T14	2652	541	0	0
T15	0	257	0	0
T16	0	5553	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T79	0	170	0	0
T82	0	608	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T9,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T100,T102
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T96,T97,T104
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T16,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	244498888	508125	0	0
DepthKnown_A	244663004	244559612	0	0
RvalidKnown_A	244663004	244559612	0	0
WreadyKnown_A	244663004	244559612	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	244663004	544605	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244498888	508125	0	0
T2	2228	283	0	0
T3	1833	191	0	0
T4	283	114	0	0
T5	350	0	0	0
T8	0	1230	0	0
T11	0	195	0	0
T14	2652	454	0	0
T15	0	186	0	0
T16	0	5518	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T79	0	38	0	0
T82	0	545	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	244559612	0	0
T1	800595	800580	0	0
T2	2228	2165	0	0
T3	1833	1770	0	0
T4	2344	2206	0	0
T14	2652	2568	0	0
T19	1943	1844	0	0
T25	1054	964	0	0
T28	2508	2444	0	0
T41	2630	2552	0	0
T44	1440	1373	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	244663004	544605	0	0
T2	2228	283	0	0
T3	1833	191	0	0
T4	2344	958	0	0
T5	1279	0	0	0
T8	0	1230	0	0
T11	0	195	0	0
T14	2652	454	0	0
T15	0	186	0	0
T16	0	5518	0	0
T19	1943	0	0	0
T25	1054	0	0	0
T28	2508	0	0	0
T41	2630	0	0	0
T44	1440	0	0	0
T79	0	38	0	0
T82	0	545	0	0