Group : tb.dut.u_edn_cov_if::edn_cs_cmd_response_cg
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Group : tb.dut.u_edn_cov_if::edn_cs_cmd_response_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
16.67 16.67 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmd_response_cg 16.67 1 100 1 64 64




Group Instance : edn_cs_cmd_response_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
16.67 1 100 1 64 64




Summary for Group Instance edn_cs_cmd_response_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 5 1 16.67


Variables for Group Instance edn_cs_cmd_response_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_csrng_rsp_sts_cg 6 5 1 16.67 100 1 1 0


Summary for Variable cp_csrng_rsp_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 6 5 1 16.67


Automatically Generated Bins for cp_csrng_rsp_sts_cg

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[CMD_STS_INVALID_ACMD] 0 1 1
auto[CMD_STS_INVALID_GEN_CMD] 0 1 1
auto[CMD_STS_INVALID_CMD_SEQ] 0 1 1
auto[CMD_STS_RESEED_CNT_EXCEEDED] 0 1 1
auto[CMD_STS_UNDRIVEN] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CMD_STS_SUCCESS] 12370 1 T1 75 T2 10 T3 7

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