Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2678	1			T1	12		T2	2		T3	1
non_zero_bins[1]	1834	1			T1	12		T2	5		T3	1
zero	9291	1			T1	51		T2	3		T3	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	501	1			T1	2		T3	1		T24	1
uni	3646	1			T1	23		T2	1		T3	2
gen	4421	1			T1	21		T2	6		T3	2
res	869	1			T1	6		T2	2		T5	2
ins	4366	1			T1	23		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9149

1

T1

46

T2

3

T3

4

mubi_true

4654

1

T1

29

T2

7

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

32

1

T50

1

T125

1

T176

1

pass

13771

1

T1

75

T2

10

T3

7

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	107	1			T39	1		T113	1		T115	1
upd	non_zero_bins[0]	pass	mubi_true	110	1			T3	1		T42	1		T65	1
upd	non_zero_bins[1]	pass	mubi_false	85	1			T24	1		T61	1		T250	1
upd	non_zero_bins[1]	pass	mubi_true	86	1			T1	1		T5	1		T52	1
upd	zero	pass	mubi_false	60	1			T44	1		T37	2		T38	1
upd	zero	pass	mubi_true	53	1			T1	1		T85	1		T38	1
uni	zero	pass	mubi_false	2733	1			T1	13		T2	1		T3	2
uni	zero	pass	mubi_true	913	1			T1	10		T5	4		T52	3
gen	non_zero_bins[0]	pass	mubi_false	539	1			T1	2		T25	1		T5	2
gen	non_zero_bins[0]	pass	mubi_true	531	1			T1	1		T2	1		T26	1
gen	non_zero_bins[1]	pass	mubi_false	329	1			T1	1		T60	1		T96	1
gen	non_zero_bins[1]	pass	mubi_true	323	1			T1	4		T2	5		T5	1
gen	zero	fail	mubi_false	27	1			T50	1		T125	1		T176	1
gen	zero	pass	mubi_false	1925	1			T1	12		T3	1		T15	1
gen	zero	pass	mubi_true	747	1			T1	1		T3	1		T15	2
res	non_zero_bins[0]	pass	mubi_false	187	1			T96	1		T116	1		T46	1
res	non_zero_bins[0]	pass	mubi_true	204	1			T1	4		T59	1		T60	1
res	non_zero_bins[1]	pass	mubi_false	135	1			T5	1		T20	2		T21	2
res	non_zero_bins[1]	pass	mubi_true	143	1			T1	2		T52	2		T22	2
res	zero	fail	mubi_false	5	1			T165	1		T166	1		T304	1
res	zero	pass	mubi_false	108	1			T2	2		T10	1		T23	1
res	zero	pass	mubi_true	87	1			T5	1		T65	1		T103	1
ins	non_zero_bins[0]	pass	mubi_false	506	1			T1	2		T5	4		T52	1
ins	non_zero_bins[0]	pass	mubi_true	494	1			T1	3		T2	1		T5	2
ins	non_zero_bins[1]	pass	mubi_false	371	1			T1	4		T24	1		T39	1
ins	non_zero_bins[1]	pass	mubi_true	362	1			T3	1		T5	1		T59	1
ins	zero	pass	mubi_false	2032	1			T1	12		T3	1		T15	1
ins	zero	pass	mubi_true	601	1			T1	2		T15	1		T4	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded