Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.14	100.00	94.44		98.65	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16	100.00	94.44		98.65	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T10,T14
1	1	Covered	T3,T15,T4

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T40
1	1	Covered	T2,T15,T16

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T9
1	0	Covered	T4,T6,T13

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T15,T16,T9
1	Covered	T4,T6,T13

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T15,T16,T9
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T15,T4,T16
1	Covered	T4,T6,T13

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	73	98.65
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T6,T10
AutoCaptGenCnt	143	Covered	T2,T9,T6
AutoCaptReseedCnt	141	Covered	T2,T10,T23
AutoDispatch	125	Covered	T2,T9,T6
AutoFirstAckWait	119	Covered	T2,T9,T6
AutoLoadIns	69	Covered	T2,T15,T16
AutoSendGenCmd	150	Covered	T2,T9,T6
AutoSendReseedCmd	162	Covered	T2,T10,T23
BootDone	98	Covered	T3,T15,T4
BootGenAckWait	90	Covered	T3,T15,T4
BootInsAckWait	80	Covered	T3,T15,T4
BootLoadGen	85	Covered	T3,T15,T4
BootLoadIns	65	Covered	T3,T15,T4
BootLoadUni	102	Covered	T3,T15,T16
BootPulse	94	Covered	T3,T15,T4
BootUniAckWait	107	Covered	T3,T15,T16
Error	188	Covered	T4,T6,T13
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T15,T16,T9
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T2,T10,T23
AutoAckWait->Error	188	Covered	T6,T124
AutoAckWait->Idle	211	Covered	T66,T69,T46
AutoAckWait->RejectCsrngEntropy	188	Covered	T10,T23,T125
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T9,T6
AutoCaptGenCnt->Error	188	Covered	T126
AutoCaptGenCnt->Idle	211	Covered	T127,T128,T129
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T130,T131,T132
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T2,T10,T23
AutoCaptReseedCnt->Error	188	Covered	T133,T134,T135
AutoCaptReseedCnt->Idle	211	Covered	T136,T137,T138
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T84,T139,T140
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T9,T6
AutoDispatch->AutoCaptReseedCnt	141	Covered	T2,T10,T23
AutoDispatch->Error	188	Covered	T141,T142,T143
AutoDispatch->Idle	138	Covered	T2,T20,T21
AutoDispatch->RejectCsrngEntropy	188	Covered	T144,T145
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T9,T6
AutoFirstAckWait->Error	188	Covered	T146,T147
AutoFirstAckWait->Idle	211	Covered	T46,T148,T149
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T102,T49,T97
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T9,T6
AutoLoadIns->Error	188	Covered	T57,T150,T151
AutoLoadIns->Idle	211	Covered	T15,T16,T50
AutoLoadIns->RejectCsrngEntropy	188	Covered	T152,T153,T154
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T6,T10
AutoSendGenCmd->Error	188	Covered	T155,T156
AutoSendGenCmd->Idle	211	Covered	T157,T158,T159
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T9,T119,T160
AutoSendReseedCmd->AutoAckWait	168	Covered	T2,T10,T23
AutoSendReseedCmd->Error	188	Covered	T161
AutoSendReseedCmd->Idle	211	Covered	T162,T163,T164
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T121,T165,T166
BootDone->BootLoadUni	102	Covered	T3,T15,T16
BootDone->Error	188	Covered	T55,T167,T168
BootDone->Idle	211	Covered	T169,T92,T170
BootDone->RejectCsrngEntropy	188	Covered	T43,T118,T171
BootGenAckWait->BootPulse	94	Covered	T3,T15,T4
BootGenAckWait->Error	188	Covered	T172,T173
BootGenAckWait->Idle	211	Covered	T14,T174,T175
BootGenAckWait->RejectCsrngEntropy	188	Covered	T50,T176,T177
BootInsAckWait->BootLoadGen	85	Covered	T3,T15,T4
BootInsAckWait->Error	188	Covered	T14,T178,T179
BootInsAckWait->Idle	211	Covered	T4,T71,T79
BootInsAckWait->RejectCsrngEntropy	188	Covered	T93,T180,T181
BootLoadGen->BootGenAckWait	90	Covered	T3,T15,T4
BootLoadGen->Error	188	Covered	T71,T182
BootLoadGen->Idle	211	Covered	T72,T91,T183
BootLoadGen->RejectCsrngEntropy	188	Covered	T184,T117,T185
BootLoadIns->BootInsAckWait	80	Covered	T3,T15,T4
BootLoadIns->Error	188	Covered	T174,T186,T187
BootLoadIns->Idle	211	Covered	T81,T188,T189
BootLoadIns->RejectCsrngEntropy	188	Covered	T112,T83,T190
BootLoadUni->BootUniAckWait	107	Covered	T3,T15,T16
BootLoadUni->Error	188	Covered	T191
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T106,T192,T193
BootPulse->BootDone	98	Covered	T3,T15,T4
BootPulse->Error	188	Covered	T194,T195,T196
BootPulse->Idle	211	Covered	T197,T198,T199
BootPulse->RejectCsrngEntropy	188	Covered	T40,T200,T201
BootUniAckWait->Error	188	Covered	T202,T203,T204
BootUniAckWait->Idle	112	Covered	T3,T9,T26
BootUniAckWait->RejectCsrngEntropy	188	Covered	T15,T16,T19
Idle->AutoLoadIns	69	Covered	T2,T15,T16
Idle->BootLoadIns	65	Covered	T3,T15,T4
Idle->Error	188	Covered	T13,T17,T18
Idle->RejectCsrngEntropy	188	Covered	T10,T23,T43
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T62,T56,T58
RejectCsrngEntropy->Idle	211	Covered	T15,T16,T9
SWPortMode->Error	188	Covered	T13,T53,T205
SWPortMode->Idle	211	Covered	T1,T5,T52
SWPortMode->RejectCsrngEntropy	188	Covered	T15,T16,T9

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T15,T16
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T15,T16
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T9,T14
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T16
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T3,T15,T16
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T15,T16
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T9,T6
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T15,T16
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T9,T6
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T9,T6
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T10,T23
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T6,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T20,T21
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T10,T23
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T9,T6
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T6
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T9,T6
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T9,T6
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T23
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T10,T23
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T10,T23
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T9
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T13,T7

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T6,T13
1	0	1	-	Not Covered
1	0	0	-	Covered	T15,T16,T9
0	-	-	1	Covered	T15,T4,T16
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	216287617	163139	0	0
FpvSecCmErrorStEscalate_A	216287617	164309	0	0
u_state_regs_A	216251888	216060565	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	163139	0	0
T4	1812	1020	0	0
T5	27360	0	0	0
T6	0	272	0	0
T7	0	1062	0	0
T9	2309	0	0	0
T13	0	18418	0	0
T14	0	418	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	288	0	0
T62	0	524	0	0
T70	0	1089	0	0
T71	0	1170	0	0
T109	0	331	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	164309	0	0
T4	1812	1021	0	0
T5	27360	0	0	0
T6	0	273	0	0
T7	0	1063	0	0
T9	2309	0	0	0
T13	0	18678	0	0
T14	0	419	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	289	0	0
T62	0	525	0	0
T70	0	1090	0	0
T71	0	1171	0	0
T109	0	332	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216251888	216060565	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1692	1511	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0