Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T197,T199,T206
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T79,T72,T91
DataWait->Error	99	Covered	T6,T14,T71
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T17,T18
EndPointClear->Disabled	107	Covered	T66,T81,T107
EndPointClear->Error	99	Covered	T4,T13,T174
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T1,T15,T4
Idle->Error	99	Covered	T6,T13,T7

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T6,T13
default	-	-	-	-	Covered	T13,T62,T71

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T13
0	1	Covered	T15,T4,T16
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1514013319	1155673	0	0
FpvSecCmErrorStEscalate_A	1514013319	1163863	0	0
u_state_regs_A	1513977590	1512638329	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514013319	1155673	0	0
T4	12684	7490	0	0
T5	191520	0	0	0
T6	0	1904	0	0
T7	0	7784	0	0
T9	16163	0	0	0
T13	0	128926	0	0
T14	0	2926	0	0
T16	16653	0	0	0
T24	13538	0	0	0
T25	19950	0	0	0
T26	10759	0	0	0
T39	23618	0	0	0
T50	19523	0	0	0
T51	10080	0	0	0
T53	0	2016	0	0
T62	0	3618	0	0
T70	0	7973	0	0
T71	0	8140	0	0
T109	0	2667	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514013319	1163863	0	0
T4	12684	7497	0	0
T5	191520	0	0	0
T6	0	1911	0	0
T7	0	7791	0	0
T9	16163	0	0	0
T13	0	130746	0	0
T14	0	2933	0	0
T16	16653	0	0	0
T24	13538	0	0	0
T25	19950	0	0	0
T26	10759	0	0	0
T39	23618	0	0	0
T50	19523	0	0	0
T51	10080	0	0	0
T53	0	2023	0	0
T62	0	3625	0	0
T70	0	7980	0	0
T71	0	8147	0	0
T109	0	2674	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513977590	1512638329	0	0
T1	2192393	2192330	0	0
T2	25648	24948	0	0
T3	13090	12614	0	0
T4	12564	11297	0	0
T9	16163	15540	0	0
T15	18732	18347	0	0
T16	16653	16268	0	0
T24	13538	13125	0	0
T25	19950	19523	0	0
T26	10759	10339	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T15
DataWait	75	Covered	T1,T2,T15
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T15
DataWait->AckPls	80	Covered	T1,T2,T15
DataWait->Disabled	107	Covered	T207,T158,T159
DataWait->Error	99	Covered	T6,T14,T109
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T17,T18
EndPointClear->Disabled	107	Covered	T66,T81,T107
EndPointClear->Error	99	Covered	T4,T13,T17
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T15
Idle->Disabled	107	Covered	T1,T15,T4
Idle->Error	99	Covered	T13,T7,T70

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T15
Idle	-	1	0	-	Covered	T1,T2,T15
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T15
DataWait	-	-	-	0	Covered	T1,T2,T15
AckPls	-	-	-	-	Covered	T1,T2,T15
Error	-	-	-	-	Covered	T4,T6,T13
default	-	-	-	-	Covered	T13,T62,T71

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T13
0	1	Covered	T15,T4,T16
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216287617	163039	0	0
FpvSecCmErrorStEscalate_A	216287617	164209	0	0
u_state_regs_A	216251888	216060565	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	163039	0	0
T4	1812	1070	0	0
T5	27360	0	0	0
T6	0	272	0	0
T7	0	1112	0	0
T9	2309	0	0	0
T13	0	18418	0	0
T14	0	418	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	288	0	0
T62	0	474	0	0
T70	0	1139	0	0
T71	0	1120	0	0
T109	0	381	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	164209	0	0
T4	1812	1071	0	0
T5	27360	0	0	0
T6	0	273	0	0
T7	0	1113	0	0
T9	2309	0	0	0
T13	0	18678	0	0
T14	0	419	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	289	0	0
T62	0	475	0	0
T70	0	1140	0	0
T71	0	1121	0	0
T109	0	382	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216251888	216060565	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1692	1511	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T25
DataWait	75	Covered	T2,T3,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T25
DataWait->AckPls	80	Covered	T2,T3,T25
DataWait->Disabled	107	Covered	T72,T127,T157
DataWait->Error	99	Covered	T71,T167,T208
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T17,T18
EndPointClear->Disabled	107	Covered	T66,T81,T107
EndPointClear->Error	99	Covered	T4,T13,T174
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T25
Idle->Disabled	107	Covered	T1,T15,T4
Idle->Error	99	Covered	T6,T13,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T25
Idle	-	1	0	-	Covered	T2,T3,T25
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T25
DataWait	-	-	-	0	Covered	T2,T3,T25
AckPls	-	-	-	-	Covered	T2,T3,T25
Error	-	-	-	-	Covered	T4,T6,T13
default	-	-	-	-	Covered	T13,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T13
0	1	Covered	T15,T4,T16
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216287617	165439	0	0
FpvSecCmErrorStEscalate_A	216287617	166609	0	0
u_state_regs_A	216287617	216096294	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	165439	0	0
T4	1812	1070	0	0
T5	27360	0	0	0
T6	0	272	0	0
T7	0	1112	0	0
T9	2309	0	0	0
T13	0	18418	0	0
T14	0	418	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	288	0	0
T62	0	524	0	0
T70	0	1139	0	0
T71	0	1170	0	0
T109	0	381	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	166609	0	0
T4	1812	1071	0	0
T5	27360	0	0	0
T6	0	273	0	0
T7	0	1113	0	0
T9	2309	0	0	0
T13	0	18678	0	0
T14	0	419	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	289	0	0
T62	0	525	0	0
T70	0	1140	0	0
T71	0	1171	0	0
T109	0	382	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T19,T41
DataWait	75	Covered	T25,T19,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T19,T41
DataWait->AckPls	80	Covered	T25,T19,T41
DataWait->Disabled	107	Covered	T209
DataWait->Error	99	Covered	T210,T179,T147
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T17,T18
EndPointClear->Disabled	107	Covered	T66,T81,T107
EndPointClear->Error	99	Covered	T4,T13,T174
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T19,T41
Idle->Disabled	107	Covered	T1,T15,T4
Idle->Error	99	Covered	T6,T13,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T19,T41
Idle	-	1	0	-	Covered	T25,T19,T41
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T19,T41
DataWait	-	-	-	0	Covered	T25,T41,T22
AckPls	-	-	-	-	Covered	T25,T19,T41
Error	-	-	-	-	Covered	T4,T6,T13
default	-	-	-	-	Covered	T13,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T13
0	1	Covered	T15,T4,T16
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216287617	165439	0	0
FpvSecCmErrorStEscalate_A	216287617	166609	0	0
u_state_regs_A	216287617	216096294	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	165439	0	0
T4	1812	1070	0	0
T5	27360	0	0	0
T6	0	272	0	0
T7	0	1112	0	0
T9	2309	0	0	0
T13	0	18418	0	0
T14	0	418	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	288	0	0
T62	0	524	0	0
T70	0	1139	0	0
T71	0	1170	0	0
T109	0	381	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	166609	0	0
T4	1812	1071	0	0
T5	27360	0	0	0
T6	0	273	0	0
T7	0	1113	0	0
T9	2309	0	0	0
T13	0	18678	0	0
T14	0	419	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	289	0	0
T62	0	525	0	0
T70	0	1140	0	0
T71	0	1171	0	0
T109	0	382	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T26,T39,T41
DataWait	75	Covered	T26,T39,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T26,T39,T41
DataWait->AckPls	80	Covered	T26,T39,T41
DataWait->Disabled	107	Covered	T211,T212
DataWait->Error	99	Covered	T141,T56,T213
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T17,T18
EndPointClear->Disabled	107	Covered	T66,T81,T107
EndPointClear->Error	99	Covered	T4,T13,T174
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T26,T39,T41
Idle->Disabled	107	Covered	T1,T15,T4
Idle->Error	99	Covered	T6,T13,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T26,T39,T41
Idle	-	1	0	-	Covered	T26,T39,T41
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T26,T39,T41
DataWait	-	-	-	0	Covered	T26,T39,T41
AckPls	-	-	-	-	Covered	T26,T39,T41
Error	-	-	-	-	Covered	T4,T6,T13
default	-	-	-	-	Covered	T13,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T13
0	1	Covered	T15,T4,T16
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216287617	165439	0	0
FpvSecCmErrorStEscalate_A	216287617	166609	0	0
u_state_regs_A	216287617	216096294	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	165439	0	0
T4	1812	1070	0	0
T5	27360	0	0	0
T6	0	272	0	0
T7	0	1112	0	0
T9	2309	0	0	0
T13	0	18418	0	0
T14	0	418	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	288	0	0
T62	0	524	0	0
T70	0	1139	0	0
T71	0	1170	0	0
T109	0	381	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	166609	0	0
T4	1812	1071	0	0
T5	27360	0	0	0
T6	0	273	0	0
T7	0	1113	0	0
T9	2309	0	0	0
T13	0	18678	0	0
T14	0	419	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	289	0	0
T62	0	525	0	0
T70	0	1140	0	0
T71	0	1171	0	0
T109	0	382	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T16,T26,T42
DataWait	75	Covered	T16,T26,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T206,T214
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T16,T26,T42
DataWait->AckPls	80	Covered	T16,T26,T42
DataWait->Disabled	107	Covered	T79,T215,T129
DataWait->Error	99	Covered	T202,T216,T173
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T17,T18
EndPointClear->Disabled	107	Covered	T66,T81,T107
EndPointClear->Error	99	Covered	T4,T13,T174
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T16,T26,T42
Idle->Disabled	107	Covered	T1,T15,T4
Idle->Error	99	Covered	T6,T13,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T16,T26,T42
Idle	-	1	0	-	Covered	T16,T26,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T16,T26,T42
DataWait	-	-	-	0	Covered	T16,T26,T42
AckPls	-	-	-	-	Covered	T16,T26,T42
Error	-	-	-	-	Covered	T4,T6,T13
default	-	-	-	-	Covered	T13,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T13
0	1	Covered	T15,T4,T16
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216287617	165439	0	0
FpvSecCmErrorStEscalate_A	216287617	166609	0	0
u_state_regs_A	216287617	216096294	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	165439	0	0
T4	1812	1070	0	0
T5	27360	0	0	0
T6	0	272	0	0
T7	0	1112	0	0
T9	2309	0	0	0
T13	0	18418	0	0
T14	0	418	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	288	0	0
T62	0	524	0	0
T70	0	1139	0	0
T71	0	1170	0	0
T109	0	381	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	166609	0	0
T4	1812	1071	0	0
T5	27360	0	0	0
T6	0	273	0	0
T7	0	1113	0	0
T9	2309	0	0	0
T13	0	18678	0	0
T14	0	419	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	289	0	0
T62	0	525	0	0
T70	0	1140	0	0
T71	0	1171	0	0
T109	0	382	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T26,T39
DataWait	75	Covered	T25,T26,T39
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T197,T217
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T26,T39
DataWait->AckPls	80	Covered	T25,T26,T39
DataWait->Disabled	107	Covered	T88,T218
DataWait->Error	99	Covered	T7,T219,T220
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T17,T18
EndPointClear->Disabled	107	Covered	T66,T81,T107
EndPointClear->Error	99	Covered	T4,T13,T174
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T26,T39
Idle->Disabled	107	Covered	T1,T15,T4
Idle->Error	99	Covered	T6,T13,T62

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T26,T39
Idle	-	1	0	-	Covered	T25,T26,T39
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T26,T39
DataWait	-	-	-	0	Covered	T25,T26,T39
AckPls	-	-	-	-	Covered	T25,T26,T39
Error	-	-	-	-	Covered	T4,T6,T13
default	-	-	-	-	Covered	T13,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T13
0	1	Covered	T15,T4,T16
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216287617	165439	0	0
FpvSecCmErrorStEscalate_A	216287617	166609	0	0
u_state_regs_A	216287617	216096294	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	165439	0	0
T4	1812	1070	0	0
T5	27360	0	0	0
T6	0	272	0	0
T7	0	1112	0	0
T9	2309	0	0	0
T13	0	18418	0	0
T14	0	418	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	288	0	0
T62	0	524	0	0
T70	0	1139	0	0
T71	0	1170	0	0
T109	0	381	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	166609	0	0
T4	1812	1071	0	0
T5	27360	0	0	0
T6	0	273	0	0
T7	0	1113	0	0
T9	2309	0	0	0
T13	0	18678	0	0
T14	0	419	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	289	0	0
T62	0	525	0	0
T70	0	1140	0	0
T71	0	1171	0	0
T109	0	382	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T40,T41,T47
DataWait	75	Covered	T40,T41,T47
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T13
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T199,T221
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T40,T41,T47
DataWait->AckPls	80	Covered	T40,T41,T47
DataWait->Disabled	107	Covered	T91,T222
DataWait->Error	99	Covered	T178,T143,T223
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T17,T18
EndPointClear->Disabled	107	Covered	T66,T81,T107
EndPointClear->Error	99	Covered	T4,T13,T174
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T40,T41,T47
Idle->Disabled	107	Covered	T1,T15,T4
Idle->Error	99	Covered	T6,T13,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T40,T41,T47
Idle	-	1	0	-	Covered	T40,T41,T47
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T40,T41,T47
DataWait	-	-	-	0	Covered	T40,T41,T47
AckPls	-	-	-	-	Covered	T40,T41,T47
Error	-	-	-	-	Covered	T4,T6,T13
default	-	-	-	-	Covered	T13,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T13
0	1	Covered	T15,T4,T16
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216287617	165439	0	0
FpvSecCmErrorStEscalate_A	216287617	166609	0	0
u_state_regs_A	216287617	216096294	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	165439	0	0
T4	1812	1070	0	0
T5	27360	0	0	0
T6	0	272	0	0
T7	0	1112	0	0
T9	2309	0	0	0
T13	0	18418	0	0
T14	0	418	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	288	0	0
T62	0	524	0	0
T70	0	1139	0	0
T71	0	1170	0	0
T109	0	381	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	166609	0	0
T4	1812	1071	0	0
T5	27360	0	0	0
T6	0	273	0	0
T7	0	1113	0	0
T9	2309	0	0	0
T13	0	18678	0	0
T14	0	419	0	0
T16	2379	0	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T39	3374	0	0	0
T50	2789	0	0	0
T51	1440	0	0	0
T53	0	289	0	0
T62	0	525	0	0
T70	0	1140	0	0
T71	0	1171	0	0
T109	0	382	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0