Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T15,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T35,T98
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T32,T31
1	0	1	Covered	T2,T15,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T6

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431799498	586853	0	0
DepthKnown_A	432575234	432192588	0	0
RvalidKnown_A	432575234	432192588	0	0
WreadyKnown_A	432575234	432192588	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	432173962	675459	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431799498	586853	0	0
T2	7328	2980	0	0
T3	3740	0	0	0
T4	252	0	0	0
T6	0	103	0	0
T7	0	218	0	0
T9	4618	420	0	0
T10	0	672	0	0
T15	5352	230	0	0
T16	4758	461	0	0
T19	0	291	0	0
T24	3868	0	0	0
T25	5700	0	0	0
T26	3074	0	0	0
T40	0	207	0	0
T50	0	134	0	0
T51	2880	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432575234	432192588	0	0
T1	626398	626380	0	0
T2	7328	7128	0	0
T3	3740	3604	0	0
T4	3624	3262	0	0
T9	4618	4440	0	0
T15	5352	5242	0	0
T16	4758	4648	0	0
T24	3868	3750	0	0
T25	5700	5578	0	0
T26	3074	2954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432575234	432192588	0	0
T1	626398	626380	0	0
T2	7328	7128	0	0
T3	3740	3604	0	0
T4	3624	3262	0	0
T9	4618	4440	0	0
T15	5352	5242	0	0
T16	4758	4648	0	0
T24	3868	3750	0	0
T25	5700	5578	0	0
T26	3074	2954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432575234	432192588	0	0
T1	626398	626380	0	0
T2	7328	7128	0	0
T3	3740	3604	0	0
T4	3624	3262	0	0
T9	4618	4440	0	0
T15	5352	5242	0	0
T16	4758	4648	0	0
T24	3868	3750	0	0
T25	5700	5578	0	0
T26	3074	2954	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	432173962	675459	0	0
T2	7328	2980	0	0
T3	3740	0	0	0
T4	3624	220	0	0
T6	0	645	0	0
T7	0	2126	0	0
T9	4618	420	0	0
T10	0	672	0	0
T15	5352	230	0	0
T16	4758	461	0	0
T19	0	291	0	0
T24	3868	0	0	0
T25	5700	0	0	0
T26	3074	0	0	0
T50	0	134	0	0
T51	2880	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T6,T66
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T15,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T98
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T31,T99
1	0	1	Covered	T2,T15,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T23

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	215899749	287244	0	0
DepthKnown_A	216287617	216096294	0	0
RvalidKnown_A	216287617	216096294	0	0
WreadyKnown_A	216287617	216096294	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216086981	330993	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215899749	287244	0	0
T2	3664	1429	0	0
T3	1870	0	0	0
T4	126	0	0	0
T6	0	51	0	0
T7	0	65	0	0
T9	2309	301	0	0
T10	0	341	0	0
T15	2676	57	0	0
T16	2379	175	0	0
T19	0	145	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T40	0	46	0	0
T50	0	28	0	0
T51	1440	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216086981	330993	0	0
T2	3664	1429	0	0
T3	1870	0	0	0
T4	1812	111	0	0
T6	0	319	0	0
T7	0	1011	0	0
T9	2309	301	0	0
T10	0	341	0	0
T15	2676	57	0	0
T16	2379	175	0	0
T19	0	145	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T50	0	28	0	0
T51	1440	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T15,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32
1	0	1	Covered	T2,T15,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	215899749	299609	0	0
DepthKnown_A	216287617	216096294	0	0
RvalidKnown_A	216287617	216096294	0	0
WreadyKnown_A	216287617	216096294	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216086981	344466	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215899749	299609	0	0
T2	3664	1551	0	0
T3	1870	0	0	0
T4	126	0	0	0
T6	0	52	0	0
T7	0	153	0	0
T9	2309	119	0	0
T10	0	331	0	0
T15	2676	173	0	0
T16	2379	286	0	0
T19	0	146	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T40	0	161	0	0
T50	0	106	0	0
T51	1440	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216287617	216096294	0	0
T1	313199	313190	0	0
T2	3664	3564	0	0
T3	1870	1802	0	0
T4	1812	1631	0	0
T9	2309	2220	0	0
T15	2676	2621	0	0
T16	2379	2324	0	0
T24	1934	1875	0	0
T25	2850	2789	0	0
T26	1537	1477	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216086981	344466	0	0
T2	3664	1551	0	0
T3	1870	0	0	0
T4	1812	109	0	0
T6	0	326	0	0
T7	0	1115	0	0
T9	2309	119	0	0
T10	0	331	0	0
T15	2676	173	0	0
T16	2379	286	0	0
T19	0	146	0	0
T24	1934	0	0	0
T25	2850	0	0	0
T26	1537	0	0	0
T50	0	106	0	0
T51	1440	0	0	0