Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	140	1			T3	1		T33	1		T48	1
auto_req_mode	143	1			T10	1		T15	1		T23	1
sw_mode	2757	1			T1	1		T2	17		T27	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

296

1

T3

1

T27

1

T28

1

single

104

1

T1

1

T48

1

T25

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1103	1			T1	1		T3	1		T28	1
auto[2]	159	1			T2	17		T324	1		T325	1
auto[3]	90	1			T26	1		T248	1		T326	1
auto[4]	42	1			T27	1		T97	1		T122	14
auto[5]	273	1			T49	1		T288	1		T121	1
auto[6]	123	1			T29	1		T23	1		T238	24
auto[7]	1250	1			T33	1		T46	1		T47	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	79	1			T3	1		T48	1		T102	1
auto[1]	auto_req_mode	88	1			T10	1		T15	1		T86	1
auto[1]	sw_mode	936	1			T1	1		T28	1		T90	1
auto[2]	boot_req_mode	6	1			T327	1		T328	1		T329	1
auto[2]	auto_req_mode	2	1			T325	1		T330	1		-	-
auto[2]	sw_mode	151	1			T2	17		T324	1		T331	1
auto[3]	boot_req_mode	3	1			T326	1		T332	1		T333	1
auto[3]	auto_req_mode	4	1			T26	1		T248	1		T334	1
auto[3]	sw_mode	83	1			T335	1		T336	11		T337	1
auto[4]	boot_req_mode	5	1			T83	1		T338	1		T339	1
auto[4]	auto_req_mode	2	1			T14	1		T340	1		-	-
auto[4]	sw_mode	35	1			T27	1		T97	1		T122	14
auto[5]	boot_req_mode	5	1			T49	1		T341	1		T342	1
auto[5]	auto_req_mode	3	1			T343	1		T344	1		T345	1
auto[5]	sw_mode	265	1			T288	1		T121	1		T116	29
auto[6]	boot_req_mode	2	1			T346	1		T347	1		-	-
auto[6]	auto_req_mode	3	1			T23	1		T348	1		T349	1
auto[6]	sw_mode	118	1			T29	1		T238	24		T53	1
auto[7]	boot_req_mode	40	1			T33	1		T54	1		T50	1
auto[7]	auto_req_mode	41	1			T25	1		T95	1		T108	1
auto[7]	sw_mode	1169	1			T46	1		T47	1		T43	26