Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	598193	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4711728

1

T1

30

T2

240

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1411392	1			T1	164		T2	438		T3	1
values[0x0]	1802306	1			T1	15		T2	125		T3	3
values[0x1]	2096223	1			T1	12		T2	98		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	299013	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5010908

1

T1

85

T2

362

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20370	1			T2	1		T19	4		T28	1
valid_sources[0x01]	20506	1			T33	1		T47	1		T49	1
valid_sources[0x02]	20039	1			T9	2		T91	1		T5	3
valid_sources[0x03]	21218	1			T9	2		T47	1		T49	1
valid_sources[0x04]	19511	1			T1	15		T2	10		T23	1
valid_sources[0x05]	20602	1			T19	4		T28	2		T9	1
valid_sources[0x06]	19249	1			T18	2		T9	2		T10	1
valid_sources[0x07]	20562	1			T43	796		T57	3		T127	1
valid_sources[0x08]	22204	1			T2	3		T28	1		T90	1
valid_sources[0x09]	19485	1			T2	4		T3	2		T9	3
valid_sources[0x0a]	20555	1			T28	1		T91	1		T39	1
valid_sources[0x0b]	20533	1			T28	1		T91	2		T6	1
valid_sources[0x0c]	19521	1			T2	4		T19	5		T91	1
valid_sources[0x0d]	21983	1			T2	4		T28	1		T9	4
valid_sources[0x0e]	20025	1			T2	6		T10	3		T6	2
valid_sources[0x0f]	19862	1			T2	3		T18	1		T28	1
valid_sources[0x10]	19427	1			T2	2		T90	2		T91	1
valid_sources[0x11]	20055	1			T19	2		T28	1		T6	1
valid_sources[0x12]	21036	1			T23	2		T43	843		T26	1
valid_sources[0x13]	21148	1			T2	4		T10	1		T91	1
valid_sources[0x14]	20687	1			T2	1		T28	1		T43	707
valid_sources[0x15]	22482	1			T2	1		T28	1		T33	3
valid_sources[0x16]	20836	1			T2	2		T90	1		T6	1
valid_sources[0x17]	19571	1			T4	4		T10	2		T54	1
valid_sources[0x18]	19885	1			T18	1		T28	1		T91	1
valid_sources[0x19]	21873	1			T1	2		T4	3		T33	2
valid_sources[0x1a]	20964	1			T6	2		T43	672		T57	1
valid_sources[0x1b]	23091	1			T2	1		T33	1		T49	1
valid_sources[0x1c]	21174	1			T2	2		T18	3		T28	1
valid_sources[0x1d]	20549	1			T2	1		T18	1		T91	3
valid_sources[0x1e]	19780	1			T2	7		T19	2		T10	1
valid_sources[0x1f]	20630	1			T18	1		T33	8		T54	1
valid_sources[0x20]	21166	1			T54	1		T43	689		T26	1
valid_sources[0x21]	21352	1			T18	1		T10	2		T49	1
valid_sources[0x22]	20893	1			T23	3		T6	1		T47	4
valid_sources[0x23]	21967	1			T2	1		T91	1		T49	1
valid_sources[0x24]	21902	1			T91	3		T47	1		T54	2
valid_sources[0x25]	20151	1			T2	3		T18	1		T19	1
valid_sources[0x26]	20409	1			T28	1		T4	1		T90	1
valid_sources[0x27]	20144	1			T2	1		T4	4		T33	6
valid_sources[0x28]	21414	1			T90	2		T23	2		T49	1
valid_sources[0x29]	19896	1			T2	8		T18	4		T4	2
valid_sources[0x2a]	22762	1			T2	2		T18	1		T11	57
valid_sources[0x2b]	21810	1			T28	1		T43	788		T24	2
valid_sources[0x2c]	21623	1			T2	4		T28	2		T9	1
valid_sources[0x2d]	22416	1			T2	2		T33	3		T23	1
valid_sources[0x2e]	22769	1			T2	1		T28	2		T33	5
valid_sources[0x2f]	20526	1			T91	1		T47	1		T54	1
valid_sources[0x30]	21340	1			T18	2		T28	1		T10	2
valid_sources[0x31]	21795	1			T2	1		T43	908		T57	1
valid_sources[0x32]	22371	1			T2	8		T10	1		T91	1
valid_sources[0x33]	21733	1			T2	11		T18	1		T28	2
valid_sources[0x34]	20775	1			T1	63		T90	2		T23	1
valid_sources[0x35]	20142	1			T10	1		T90	4		T54	1
valid_sources[0x36]	19820	1			T2	2		T10	1		T43	746
valid_sources[0x37]	19682	1			T19	2		T10	1		T23	1
valid_sources[0x38]	20490	1			T15	163		T47	7		T49	4
valid_sources[0x39]	19593	1			T90	1		T23	1		T6	1
valid_sources[0x3a]	22730	1			T2	15		T18	1		T19	1
valid_sources[0x3b]	20219	1			T2	10		T18	2		T4	1
valid_sources[0x3c]	19985	1			T9	3		T91	2		T6	1
valid_sources[0x3d]	20909	1			T2	2		T23	1		T47	2
valid_sources[0x3e]	20866	1			T9	1		T10	1		T92	17
valid_sources[0x3f]	20792	1			T2	2		T18	1		T28	1
valid_sources[0x40]	20237	1			T9	1		T33	4		T91	1
valid_sources[0x41]	22842	1			T2	5		T28	2		T90	1
valid_sources[0x42]	22462	1			T2	10		T18	1		T10	2
valid_sources[0x43]	19327	1			T2	7		T4	3		T10	1
valid_sources[0x44]	20074	1			T91	1		T47	1		T103	1
valid_sources[0x45]	20277	1			T103	2		T43	725		T57	3
valid_sources[0x46]	20252	1			T19	4		T33	2		T90	3
valid_sources[0x47]	20723	1			T18	3		T90	1		T43	653
valid_sources[0x48]	20514	1			T9	1		T33	15		T47	1
valid_sources[0x49]	21481	1			T2	8		T5	1		T23	2
valid_sources[0x4a]	19485	1			T9	1		T23	1		T6	1
valid_sources[0x4b]	21313	1			T28	1		T10	1		T23	1
valid_sources[0x4c]	20752	1			T28	2		T23	4		T6	1
valid_sources[0x4d]	19675	1			T2	9		T10	1		T90	1
valid_sources[0x4e]	19956	1			T2	6		T47	1		T103	2
valid_sources[0x4f]	21658	1			T2	3		T18	1		T28	1
valid_sources[0x50]	20191	1			T2	3		T18	1		T28	2
valid_sources[0x51]	20732	1			T2	3		T10	1		T91	1
valid_sources[0x52]	20998	1			T9	4		T49	2		T43	817
valid_sources[0x53]	20407	1			T2	2		T28	1		T9	1
valid_sources[0x54]	21544	1			T2	8		T47	2		T43	787
valid_sources[0x55]	20387	1			T28	1		T91	2		T46	153
valid_sources[0x56]	22140	1			T1	11		T2	7		T33	2
valid_sources[0x57]	21676	1			T2	16		T18	2		T19	4
valid_sources[0x58]	19111	1			T2	1		T90	5		T43	755
valid_sources[0x59]	21689	1			T28	1		T43	743		T56	2
valid_sources[0x5a]	20706	1			T2	6		T18	1		T28	1
valid_sources[0x5b]	21039	1			T2	1		T33	9		T54	1
valid_sources[0x5c]	20085	1			T18	1		T10	3		T39	1
valid_sources[0x5d]	20369	1			T23	1		T49	2		T103	2
valid_sources[0x5e]	19950	1			T2	2		T47	3		T49	1
valid_sources[0x5f]	21238	1			T2	5		T28	1		T9	1
valid_sources[0x60]	20444	1			T28	1		T33	2		T10	1
valid_sources[0x61]	20524	1			T9	1		T10	1		T91	1
valid_sources[0x62]	21432	1			T2	8		T91	1		T23	3
valid_sources[0x63]	20940	1			T2	3		T33	2		T6	1
valid_sources[0x64]	20836	1			T18	2		T10	2		T23	2
valid_sources[0x65]	21117	1			T91	1		T23	1		T54	1
valid_sources[0x66]	19514	1			T49	2		T43	812		T56	1
valid_sources[0x67]	20666	1			T2	8		T18	1		T90	1
valid_sources[0x68]	21252	1			T18	2		T4	2		T9	4
valid_sources[0x69]	19246	1			T2	1		T90	3		T91	1
valid_sources[0x6a]	25889	1			T18	1		T19	1		T28	1
valid_sources[0x6b]	18604	1			T2	6		T28	1		T4	3
valid_sources[0x6c]	21269	1			T19	2		T6	1		T49	2
valid_sources[0x6d]	20645	1			T2	4		T91	1		T49	1
valid_sources[0x6e]	20075	1			T10	1		T91	1		T49	1
valid_sources[0x6f]	21438	1			T2	12		T9	1		T10	2
valid_sources[0x70]	19619	1			T90	1		T91	1		T5	1
valid_sources[0x71]	22642	1			T33	5		T23	2		T47	1
valid_sources[0x72]	19953	1			T2	7		T10	2		T6	1
valid_sources[0x73]	21720	1			T33	12		T91	1		T47	1
valid_sources[0x74]	19792	1			T2	5		T18	2		T6	1
valid_sources[0x75]	18930	1			T2	3		T18	1		T19	1
valid_sources[0x76]	20977	1			T2	4		T91	2		T43	808
valid_sources[0x77]	21580	1			T33	5		T90	2		T91	1
valid_sources[0x78]	20407	1			T9	2		T10	2		T90	6
valid_sources[0x79]	21312	1			T2	5		T3	3		T33	10
valid_sources[0x7a]	21020	1			T33	2		T91	1		T48	6
valid_sources[0x7b]	20170	1			T2	8		T28	1		T23	2
valid_sources[0x7c]	20037	1			T2	16		T10	1		T90	1
valid_sources[0x7d]	21449	1			T54	1		T43	761		T26	1
valid_sources[0x7e]	20509	1			T18	2		T28	2		T9	1
valid_sources[0x7f]	21617	1			T90	1		T6	1		T103	1
valid_sources[0x80]	23516	1			T2	4		T33	9		T39	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1187068

1

T1

7

T2

94

T3

1

values[0x0]

all_enables

biggest_size

1763475

1

T1

13

T2

78

T3

1

values[0x1]

all_enables

biggest_size

1761185

1

T1

10

T2

68

T3

1