Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2609	1			T1	2		T2	7		T27	3
non_zero_bins[1]	1909	1			T1	1		T2	3		T28	2
zero	8993	1			T1	2		T2	46		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	518	1			T2	2		T33	1		T91	1
uni	3568	1			T1	2		T2	18		T27	1
gen	4288	1			T1	1		T2	17		T3	1
res	831	1			T2	1		T27	1		T10	5
ins	4306	1			T1	2		T2	18		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8902

1

T1

3

T2

44

T3

1

mubi_true

4609

1

T1

2

T2

12

T3

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

34

1

T19

1

T56

1

T128

1

pass

13477

1

T1

5

T2

56

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	130	1			T2	1		T43	1		T87	1
upd	non_zero_bins[0]	pass	mubi_true	112	1			T54	1		T43	2		T51	1
upd	non_zero_bins[1]	pass	mubi_false	92	1			T43	1		T67	1		T296	1
upd	non_zero_bins[1]	pass	mubi_true	83	1			T91	1		T120	1		T122	1
upd	zero	pass	mubi_false	56	1			T33	1		T43	1		T297	1
upd	zero	pass	mubi_true	45	1			T2	1		T43	2		T298	1
uni	zero	pass	mubi_false	2656	1			T1	2		T2	12		T27	1
uni	zero	pass	mubi_true	912	1			T2	6		T103	1		T43	6
gen	non_zero_bins[0]	pass	mubi_false	516	1			T2	2		T27	1		T15	4
gen	non_zero_bins[0]	pass	mubi_true	452	1			T1	1		T29	1		T10	3
gen	non_zero_bins[1]	pass	mubi_false	370	1			T28	1		T90	1		T54	1
gen	non_zero_bins[1]	pass	mubi_true	364	1			T2	1		T33	1		T23	4
gen	zero	fail	mubi_false	29	1			T19	1		T56	1		T299	1
gen	zero	pass	mubi_false	1800	1			T2	13		T3	1		T18	1
gen	zero	pass	mubi_true	757	1			T2	1		T18	2		T19	2
res	non_zero_bins[0]	pass	mubi_false	211	1			T10	5		T46	1		T43	1
res	non_zero_bins[0]	pass	mubi_true	176	1			T27	1		T15	2		T25	2
res	non_zero_bins[1]	pass	mubi_false	115	1			T2	1		T43	2		T97	1
res	non_zero_bins[1]	pass	mubi_true	142	1			T23	2		T49	1		T43	2
res	zero	fail	mubi_false	5	1			T128	1		T173	1		T300	1
res	zero	pass	mubi_false	97	1			T11	1		T43	1		T26	2
res	zero	pass	mubi_true	85	1			T124	1		T123	3		T248	2
ins	non_zero_bins[0]	pass	mubi_false	509	1			T2	2		T27	1		T29	1
ins	non_zero_bins[0]	pass	mubi_true	503	1			T1	1		T2	2		T49	1
ins	non_zero_bins[1]	pass	mubi_false	344	1			T1	1		T29	1		T90	1
ins	non_zero_bins[1]	pass	mubi_true	399	1			T2	1		T28	1		T33	1
ins	zero	pass	mubi_false	1972	1			T2	13		T18	1		T19	1
ins	zero	pass	mubi_true	579	1			T3	2		T18	1		T19	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded