Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T3,T5,T39
1	1	Covered	T3,T18,T19

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T9,T10,T6
1	1	Covered	T18,T19,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T9
1	0	Covered	T4,T5,T39

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T9
1	Covered	T4,T5,T39

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T18,T19,T9
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T18,T19,T4
1	Covered	T4,T5,T39

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T19

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T10,T11,T15
AutoCaptGenCnt	143	Covered	T10,T11,T15
AutoCaptReseedCnt	141	Covered	T10,T11,T15
AutoDispatch	125	Covered	T9,T10,T11
AutoFirstAckWait	119	Covered	T9,T10,T11
AutoLoadIns	69	Covered	T18,T19,T9
AutoSendGenCmd	150	Covered	T10,T11,T15
AutoSendReseedCmd	162	Covered	T10,T11,T15
BootDone	98	Covered	T3,T18,T33
BootGenAckWait	90	Covered	T3,T18,T19
BootInsAckWait	80	Covered	T3,T18,T19
BootLoadGen	85	Covered	T3,T18,T19
BootLoadIns	65	Covered	T3,T18,T19
BootLoadUni	102	Covered	T18,T33,T49
BootPulse	94	Covered	T3,T18,T33
BootUniAckWait	107	Covered	T33,T49,T54
Error	188	Covered	T4,T5,T39
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T18,T19,T9
SWPortMode	74	Covered	T1,T2,T18

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T10,T11,T15
AutoAckWait->Error	188	Covered	T139,T140,T141
AutoAckWait->Idle	211	Covered	T10,T86,T88
AutoAckWait->RejectCsrngEntropy	188	Covered	T11,T66,T100
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T10,T11,T15
AutoCaptGenCnt->Error	188	Covered	T142
AutoCaptGenCnt->Idle	211	Covered	T86,T143,T144
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T55,T145,T146
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T10,T11,T15
AutoCaptReseedCnt->Error	188	Covered	T147,T148,T149
AutoCaptReseedCnt->Idle	211	Covered	T10,T96,T150
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T151,T80,T152
AutoDispatch->AutoCaptGenCnt	143	Covered	T10,T11,T15
AutoDispatch->AutoCaptReseedCnt	141	Covered	T10,T11,T15
AutoDispatch->Error	188	Covered	T153,T154,T155
AutoDispatch->Idle	138	Covered	T15,T23,T25
AutoDispatch->RejectCsrngEntropy	188	Covered	T9,T156,T157
AutoFirstAckWait->AutoDispatch	125	Covered	T9,T10,T11
AutoFirstAckWait->Error	188	Covered	T64,T158
AutoFirstAckWait->Idle	211	Covered	T88,T105,T159
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T135,T160,T161
AutoLoadIns->AutoFirstAckWait	119	Covered	T9,T10,T11
AutoLoadIns->Error	188	Covered	T7,T8,T58
AutoLoadIns->Idle	211	Covered	T18,T19,T6
AutoLoadIns->RejectCsrngEntropy	188	Covered	T70,T162,T163
AutoSendGenCmd->AutoAckWait	156	Covered	T10,T11,T15
AutoSendGenCmd->Error	188	Not Covered
AutoSendGenCmd->Idle	211	Covered	T164,T165
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T166,T167,T168
AutoSendReseedCmd->AutoAckWait	168	Covered	T10,T11,T15
AutoSendReseedCmd->Error	188	Covered	T59,T169,T134
AutoSendReseedCmd->Idle	211	Covered	T170,T171,T172
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T128,T133,T173
BootDone->BootLoadUni	102	Covered	T18,T33,T49
BootDone->Error	188	Covered	T93,T174,T175
BootDone->Idle	211	Covered	T176,T17,T177
BootDone->RejectCsrngEntropy	188	Covered	T68,T178,T179
BootGenAckWait->BootPulse	94	Covered	T3,T18,T33
BootGenAckWait->Error	188	Covered	T180
BootGenAckWait->Idle	211	Covered	T181,T174,T62
BootGenAckWait->RejectCsrngEntropy	188	Covered	T19,T56,T137
BootInsAckWait->BootLoadGen	85	Covered	T3,T18,T19
BootInsAckWait->Error	188	Covered	T16,T17,T182
BootInsAckWait->Idle	211	Covered	T3,T5,T39
BootInsAckWait->RejectCsrngEntropy	188	Covered	T183,T184,T185
BootLoadGen->BootGenAckWait	90	Covered	T3,T18,T19
BootLoadGen->Error	188	Covered	T39,T92,T186
BootLoadGen->Idle	211	Covered	T48,T187,T188
BootLoadGen->RejectCsrngEntropy	188	Covered	T189,T190,T191
BootLoadIns->BootInsAckWait	80	Covered	T3,T18,T19
BootLoadIns->Error	188	Covered	T62,T192,T193
BootLoadIns->Idle	211	Covered	T102,T194,T195
BootLoadIns->RejectCsrngEntropy	188	Covered	T196,T197,T198
BootLoadUni->BootUniAckWait	107	Covered	T33,T49,T54
BootLoadUni->Error	188	Covered	T199
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T18,T119,T200
BootPulse->BootDone	98	Covered	T3,T18,T33
BootPulse->Error	188	Not Covered
BootPulse->Idle	211	Covered	T107,T201,T202
BootPulse->RejectCsrngEntropy	188	Covered	T203,T204,T205
BootUniAckWait->Error	188	Covered	T206
BootUniAckWait->Idle	112	Covered	T33,T49,T54
BootUniAckWait->RejectCsrngEntropy	188	Covered	T98,T101,T136
Idle->AutoLoadIns	69	Covered	T18,T19,T9
Idle->BootLoadIns	65	Covered	T3,T18,T19
Idle->Error	188	Covered	T20,T21,T22
Idle->RejectCsrngEntropy	188	Covered	T18,T19,T9
Idle->SWPortMode	74	Covered	T1,T2,T18
RejectCsrngEntropy->Error	188	Covered	T207,T208,T209
RejectCsrngEntropy->Idle	211	Covered	T18,T19,T9
SWPortMode->Error	188	Covered	T210,T211,T212
SWPortMode->Idle	211	Covered	T2,T9,T11
SWPortMode->RejectCsrngEntropy	188	Covered	T55,T56,T128

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T33
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T18,T33,T49
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T3,T5,T39
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T33,T49
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T33,T49,T54
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T33,T49,T54
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T10,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T18,T19,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T9,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T9,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T11,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T10,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T15,T23,T25
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T10,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T9,T10,T11
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T10,T11,T15
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T11,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T11,T15
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T9
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T39
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T5,T39
1	0	1	-	Not Covered
1	0	0	-	Covered	T18,T19,T9
0	-	-	1	Covered	T3,T18,T19
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	195149815	132178	0	0
FpvSecCmErrorStEscalate_A	195149815	132960	0	0
u_state_regs_A	195117032	194960360	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	132178	0	0
T4	895	308	0	0
T5	1146	576	0	0
T6	0	251	0	0
T7	0	346	0	0
T8	0	384	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	590	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1110	0	0
T93	0	590	0	0
T181	0	176	0	0
T210	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	132960	0	0
T4	895	309	0	0
T5	1146	577	0	0
T6	0	252	0	0
T7	0	347	0	0
T8	0	385	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	591	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1111	0	0
T93	0	591	0	0
T181	0	177	0	0
T210	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195117032	194960360	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	747	598	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0