Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	95.71	100.00	100.00		78.57	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T19

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T39
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T107,T201,T213
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T3,T48,T86
DataWait->Error	99	Covered	T5,T92,T6
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T102,T87,T194
EndPointClear->Error	99	Covered	T214,T58,T215
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T2,T3,T18
Idle->Error	99	Covered	T4,T5,T39

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T5,T39
default	-	-	-	-	Covered	T39,T92,T93

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T39
0	1	Covered	T3,T18,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1366048705	936746	0	0
FpvSecCmErrorStEscalate_A	1366048705	942220	0	0
u_state_regs_A	1366015922	1364919218	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366048705	936746	0	0
T4	6265	2506	0	0
T5	8022	4382	0	0
T6	0	2107	0	0
T7	0	2422	0	0
T8	0	2638	0	0
T9	16198	0	0	0
T10	23709	0	0	0
T11	11102	0	0	0
T33	25851	0	0	0
T39	7679	4080	0	0
T90	24752	0	0	0
T91	39340	0	0	0
T92	14175	7720	0	0
T93	0	4080	0	0
T181	0	1582	0	0
T210	0	1140	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366048705	942220	0	0
T4	6265	2513	0	0
T5	8022	4389	0	0
T6	0	2114	0	0
T7	0	2429	0	0
T8	0	2645	0	0
T9	16198	0	0	0
T10	23709	0	0	0
T11	11102	0	0	0
T33	25851	0	0	0
T39	7679	4087	0	0
T90	24752	0	0	0
T91	39340	0	0	0
T92	14175	7727	0	0
T93	0	4087	0	0
T181	0	1589	0	0
T210	0	1147	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1366015922	1364919218	0	0
T1	18529	17962	0	0
T2	225841	220584	0	0
T3	6237	5663	0	0
T4	6117	5074	0	0
T9	16198	15827	0	0
T18	18130	17591	0	0
T19	16548	16079	0	0
T27	22967	22414	0	0
T28	17213	16569	0	0
T29	27671	27125	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T27,T23,T46
DataWait	75	Covered	T27,T39,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T39
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T27,T23,T46
DataWait->AckPls	80	Covered	T27,T23,T46
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T39,T17,T182
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T102,T87,T194
EndPointClear->Error	99	Covered	T214,T58,T215
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T27,T39,T23
Idle->Disabled	107	Covered	T2,T3,T18
Idle->Error	99	Covered	T4,T5,T92

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T27,T23,T46
Idle	-	1	0	-	Covered	T27,T39,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T27,T23,T46
DataWait	-	-	-	0	Covered	T27,T39,T23
AckPls	-	-	-	-	Covered	T27,T23,T46
Error	-	-	-	-	Covered	T4,T5,T39
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T39
0	1	Covered	T3,T18,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195149815	134178	0	0
FpvSecCmErrorStEscalate_A	195149815	134960	0	0
u_state_regs_A	195149815	194993143	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134178	0	0
T4	895	358	0	0
T5	1146	626	0	0
T6	0	301	0	0
T7	0	346	0	0
T8	0	384	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	590	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1110	0	0
T93	0	590	0	0
T181	0	226	0	0
T210	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134960	0	0
T4	895	359	0	0
T5	1146	627	0	0
T6	0	302	0	0
T7	0	347	0	0
T8	0	385	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	591	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1111	0	0
T93	0	591	0	0
T181	0	227	0	0
T210	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T39
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T3,T144,T216
DataWait->Error	99	Covered	T5,T6,T7
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T102,T87,T194
EndPointClear->Error	99	Covered	T214,T58,T62
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T2,T18,T19
Idle->Error	99	Covered	T4,T217,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T5,T39
default	-	-	-	-	Covered	T39,T92,T93

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T39
0	1	Covered	T3,T18,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195149815	131678	0	0
FpvSecCmErrorStEscalate_A	195149815	132460	0	0
u_state_regs_A	195117032	194960360	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	131678	0	0
T4	895	358	0	0
T5	1146	626	0	0
T6	0	301	0	0
T7	0	346	0	0
T8	0	334	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	540	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1060	0	0
T93	0	540	0	0
T181	0	226	0	0
T210	0	120	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	132460	0	0
T4	895	359	0	0
T5	1146	627	0	0
T6	0	302	0	0
T7	0	347	0	0
T8	0	335	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	541	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1061	0	0
T93	0	541	0	0
T181	0	227	0	0
T210	0	121	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195117032	194960360	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	747	598	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T29,T4,T9
DataWait	75	Covered	T29,T4,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T39
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T29,T4,T9
DataWait->AckPls	80	Covered	T29,T4,T9
DataWait->Disabled	107	Covered	T143,T218
DataWait->Error	99	Covered	T92,T219,T180
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T102,T87,T194
EndPointClear->Error	99	Covered	T214,T58,T215
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T29,T4,T9
Idle->Disabled	107	Covered	T2,T3,T18
Idle->Error	99	Covered	T4,T5,T39

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T29,T4,T9
Idle	-	1	0	-	Covered	T29,T4,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T29,T4,T9
DataWait	-	-	-	0	Covered	T29,T9,T33
AckPls	-	-	-	-	Covered	T29,T4,T9
Error	-	-	-	-	Covered	T4,T5,T39
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T39
0	1	Covered	T3,T18,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195149815	134178	0	0
FpvSecCmErrorStEscalate_A	195149815	134960	0	0
u_state_regs_A	195149815	194993143	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134178	0	0
T4	895	358	0	0
T5	1146	626	0	0
T6	0	301	0	0
T7	0	346	0	0
T8	0	384	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	590	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1110	0	0
T93	0	590	0	0
T181	0	226	0	0
T210	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134960	0	0
T4	895	359	0	0
T5	1146	627	0	0
T6	0	302	0	0
T7	0	347	0	0
T8	0	385	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	591	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1111	0	0
T93	0	591	0	0
T181	0	227	0	0
T210	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T27,T19,T33
DataWait	75	Covered	T27,T19,T33
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T39
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T27,T19,T33
DataWait->AckPls	80	Covered	T27,T19,T33
DataWait->Disabled	107	Covered	T220
DataWait->Error	99	Covered	T16,T221,T222
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T102,T87,T194
EndPointClear->Error	99	Covered	T214,T58,T215
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T27,T19,T33
Idle->Disabled	107	Covered	T2,T3,T18
Idle->Error	99	Covered	T4,T5,T39

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T27,T19,T33
Idle	-	1	0	-	Covered	T27,T19,T33
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T27,T19,T33
DataWait	-	-	-	0	Covered	T27,T19,T33
AckPls	-	-	-	-	Covered	T27,T19,T33
Error	-	-	-	-	Covered	T4,T5,T39
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T39
0	1	Covered	T3,T18,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195149815	134178	0	0
FpvSecCmErrorStEscalate_A	195149815	134960	0	0
u_state_regs_A	195149815	194993143	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134178	0	0
T4	895	358	0	0
T5	1146	626	0	0
T6	0	301	0	0
T7	0	346	0	0
T8	0	384	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	590	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1110	0	0
T93	0	590	0	0
T181	0	226	0	0
T210	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134960	0	0
T4	895	359	0	0
T5	1146	627	0	0
T6	0	302	0	0
T7	0	347	0	0
T8	0	385	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	591	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1111	0	0
T93	0	591	0	0
T181	0	227	0	0
T210	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T46,T47
DataWait	75	Covered	T23,T46,T47
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T39
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T223
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T46,T47
DataWait->AckPls	80	Covered	T23,T46,T47
DataWait->Disabled	107	Covered	T188,T224,T225
DataWait->Error	99	Covered	T93,T174,T226
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T102,T87,T194
EndPointClear->Error	99	Covered	T214,T58,T215
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T46,T47
Idle->Disabled	107	Covered	T2,T3,T18
Idle->Error	99	Covered	T4,T5,T39

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T46,T47
Idle	-	1	0	-	Covered	T23,T46,T47
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T46,T47
DataWait	-	-	-	0	Covered	T23,T46,T47
AckPls	-	-	-	-	Covered	T23,T46,T47
Error	-	-	-	-	Covered	T4,T5,T39
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T39
0	1	Covered	T3,T18,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195149815	134178	0	0
FpvSecCmErrorStEscalate_A	195149815	134960	0	0
u_state_regs_A	195149815	194993143	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134178	0	0
T4	895	358	0	0
T5	1146	626	0	0
T6	0	301	0	0
T7	0	346	0	0
T8	0	384	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	590	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1110	0	0
T93	0	590	0	0
T181	0	226	0	0
T210	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134960	0	0
T4	895	359	0	0
T5	1146	627	0	0
T6	0	302	0	0
T7	0	347	0	0
T8	0	385	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	591	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1111	0	0
T93	0	591	0	0
T181	0	227	0	0
T210	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T46,T47,T25
DataWait	75	Covered	T46,T47,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T39
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T213,T227
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T46,T47,T25
DataWait->AckPls	80	Covered	T46,T47,T25
DataWait->Disabled	107	Covered	T86,T164,T228
DataWait->Error	99	Covered	T64,T229,T142
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T102,T87,T194
EndPointClear->Error	99	Covered	T214,T58,T215
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T46,T47,T25
Idle->Disabled	107	Covered	T2,T3,T18
Idle->Error	99	Covered	T4,T5,T39

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T46,T47,T25
Idle	-	1	0	-	Covered	T46,T47,T25
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T46,T47,T25
DataWait	-	-	-	0	Covered	T46,T47,T25
AckPls	-	-	-	-	Covered	T46,T47,T25
Error	-	-	-	-	Covered	T4,T5,T39
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T39
0	1	Covered	T3,T18,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195149815	134178	0	0
FpvSecCmErrorStEscalate_A	195149815	134960	0	0
u_state_regs_A	195149815	194993143	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134178	0	0
T4	895	358	0	0
T5	1146	626	0	0
T6	0	301	0	0
T7	0	346	0	0
T8	0	384	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	590	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1110	0	0
T93	0	590	0	0
T181	0	226	0	0
T210	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134960	0	0
T4	895	359	0	0
T5	1146	627	0	0
T6	0	302	0	0
T7	0	347	0	0
T8	0	385	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	591	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1111	0	0
T93	0	591	0	0
T181	0	227	0	0
T210	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T18,T33,T48
DataWait	75	Covered	T18,T33,T48
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T39
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T107,T201
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T18,T33,T48
DataWait->AckPls	80	Covered	T18,T33,T48
DataWait->Disabled	107	Covered	T48,T187,T230
DataWait->Error	99	Covered	T209,T231,T232
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T102,T87,T194
EndPointClear->Error	99	Covered	T214,T58,T215
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T18,T33,T48
Idle->Disabled	107	Covered	T2,T3,T18
Idle->Error	99	Covered	T4,T5,T39

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T18,T33,T48
Idle	-	1	0	-	Covered	T18,T33,T48
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T18,T33,T48
DataWait	-	-	-	0	Covered	T18,T33,T48
AckPls	-	-	-	-	Covered	T18,T33,T48
Error	-	-	-	-	Covered	T4,T5,T39
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T39
0	1	Covered	T3,T18,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195149815	134178	0	0
FpvSecCmErrorStEscalate_A	195149815	134960	0	0
u_state_regs_A	195149815	194993143	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134178	0	0
T4	895	358	0	0
T5	1146	626	0	0
T6	0	301	0	0
T7	0	346	0	0
T8	0	384	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	590	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1110	0	0
T93	0	590	0	0
T181	0	226	0	0
T210	0	170	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	134960	0	0
T4	895	359	0	0
T5	1146	627	0	0
T6	0	302	0	0
T7	0	347	0	0
T8	0	385	0	0
T9	2314	0	0	0
T10	3387	0	0	0
T11	1586	0	0	0
T33	3693	0	0	0
T39	1097	591	0	0
T90	3536	0	0	0
T91	5620	0	0	0
T92	2025	1111	0	0
T93	0	591	0	0
T181	0	227	0	0
T210	0	171	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0