Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T19,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T37,T38,T109
1	1	0	Not Covered
1	1	1	Covered	T18,T19,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T40,T41,T42
1	0	1	Covered	T18,T19,T9
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T15

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	389674516	1069565	0	0
DepthKnown_A	390299630	389986286	0	0
RvalidKnown_A	390299630	389986286	0	0
WreadyKnown_A	390299630	389986286	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	390021050	1148062	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389674516	1069565	0	0
T4	624	0	0	0
T6	0	409	0	0
T9	4628	547	0	0
T10	6774	4116	0	0
T11	0	364	0	0
T15	0	5073	0	0
T18	5180	580	0	0
T19	4728	215	0	0
T23	0	6531	0	0
T25	0	12824	0	0
T26	0	479	0	0
T27	6562	0	0	0
T28	4918	0	0	0
T29	7906	0	0	0
T33	7386	0	0	0
T90	7072	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390299630	389986286	0	0
T1	5294	5132	0	0
T2	64526	63024	0	0
T3	1782	1618	0	0
T4	1790	1492	0	0
T9	4628	4522	0	0
T18	5180	5026	0	0
T19	4728	4594	0	0
T27	6562	6404	0	0
T28	4918	4734	0	0
T29	7906	7750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390299630	389986286	0	0
T1	5294	5132	0	0
T2	64526	63024	0	0
T3	1782	1618	0	0
T4	1790	1492	0	0
T9	4628	4522	0	0
T18	5180	5026	0	0
T19	4728	4594	0	0
T27	6562	6404	0	0
T28	4918	4734	0	0
T29	7906	7750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390299630	389986286	0	0
T1	5294	5132	0	0
T2	64526	63024	0	0
T3	1782	1618	0	0
T4	1790	1492	0	0
T9	4628	4522	0	0
T18	5180	5026	0	0
T19	4728	4594	0	0
T27	6562	6404	0	0
T28	4918	4734	0	0
T29	7906	7750	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	390021050	1148062	0	0
T4	1790	0	0	0
T5	0	241	0	0
T9	4628	547	0	0
T10	6774	4116	0	0
T11	0	364	0	0
T15	0	5073	0	0
T18	5180	580	0	0
T19	4728	215	0	0
T23	0	6531	0	0
T27	6562	0	0	0
T28	4918	0	0	0
T29	7906	0	0	0
T33	7386	0	0	0
T39	0	292	0	0
T90	7072	0	0	0
T92	0	292	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T110,T111
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T19,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T109
1	1	0	Not Covered
1	1	1	Covered	T18,T19,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T40,T41,T112
1	0	1	Covered	T18,T19,T9
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	194837258	528933	0	0
DepthKnown_A	195149815	194993143	0	0
RvalidKnown_A	195149815	194993143	0	0
WreadyKnown_A	195149815	194993143	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	195010525	567963	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194837258	528933	0	0
T4	312	0	0	0
T6	0	213	0	0
T9	2314	265	0	0
T10	3387	1913	0	0
T11	0	183	0	0
T15	0	2530	0	0
T18	2590	262	0	0
T19	2364	60	0	0
T23	0	3262	0	0
T25	0	6364	0	0
T26	0	226	0	0
T27	3281	0	0	0
T28	2459	0	0	0
T29	3953	0	0	0
T33	3693	0	0	0
T90	3536	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	195010525	567963	0	0
T4	895	0	0	0
T5	0	123	0	0
T9	2314	265	0	0
T10	3387	1913	0	0
T11	0	183	0	0
T15	0	2530	0	0
T18	2590	262	0	0
T19	2364	60	0	0
T23	0	3262	0	0
T27	3281	0	0	0
T28	2459	0	0	0
T29	3953	0	0	0
T33	3693	0	0	0
T39	0	147	0	0
T90	3536	0	0	0
T92	0	147	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T19,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T37,T38,T113
1	1	0	Not Covered
1	1	1	Covered	T18,T19,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T42,T114,T115
1	0	1	Covered	T18,T19,T9
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	194837258	540632	0	0
DepthKnown_A	195149815	194993143	0	0
RvalidKnown_A	195149815	194993143	0	0
WreadyKnown_A	195149815	194993143	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	195010525	580099	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194837258	540632	0	0
T4	312	0	0	0
T6	0	196	0	0
T9	2314	282	0	0
T10	3387	2203	0	0
T11	0	181	0	0
T15	0	2543	0	0
T18	2590	318	0	0
T19	2364	155	0	0
T23	0	3269	0	0
T25	0	6460	0	0
T26	0	253	0	0
T27	3281	0	0	0
T28	2459	0	0	0
T29	3953	0	0	0
T33	3693	0	0	0
T90	3536	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195149815	194993143	0	0
T1	2647	2566	0	0
T2	32263	31512	0	0
T3	891	809	0	0
T4	895	746	0	0
T9	2314	2261	0	0
T18	2590	2513	0	0
T19	2364	2297	0	0
T27	3281	3202	0	0
T28	2459	2367	0	0
T29	3953	3875	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	195010525	580099	0	0
T4	895	0	0	0
T5	0	118	0	0
T9	2314	282	0	0
T10	3387	2203	0	0
T11	0	181	0	0
T15	0	2543	0	0
T18	2590	318	0	0
T19	2364	155	0	0
T23	0	3269	0	0
T27	3281	0	0	0
T28	2459	0	0	0
T29	3953	0	0	0
T33	3693	0	0	0
T39	0	145	0	0
T90	3536	0	0	0
T92	0	145	0	0