Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.97	96.97	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	96.97	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.97	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	1	20	95.24

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	1	20	95.24	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	153	1			T44	1		T74	1		T39	1
auto_req_mode	137	1			T10	1		T15	1		T20	1
sw_mode	2788	1			T24	1		T6	71		T25	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

294

1

T24

1

T10

1

T44

1

single

105

1

T83

1

T105

1

T78

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1472	1			T10	1		T25	1		T65	1
auto[2]	129	1			T6	71		T46	1		T98	14
auto[3]	68	1			T39	1		T40	1		T295	1
auto[4]	87	1			T49	1		T233	71		T317	1
auto[5]	215	1			T57	6		T318	1		T51	1
auto[6]	27	1			T319	1		T250	1		T320	1
auto[7]	1080	1			T24	1		T41	1		T43	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	1	20	95.24	1

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[4]]	[auto_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	88	1			T44	1		T74	1		T68	1
auto[1]	auto_req_mode	82	1			T10	1		T15	1		T20	1
auto[1]	sw_mode	1302	1			T25	1		T65	1		T73	1
auto[2]	boot_req_mode	3	1			T321	1		T322	1		T323	1
auto[2]	auto_req_mode	5	1			T324	1		T325	1		T326	1
auto[2]	sw_mode	121	1			T6	71		T46	1		T98	14
auto[3]	boot_req_mode	6	1			T39	1		T40	1		T295	1
auto[3]	auto_req_mode	3	1			T327	1		T328	1		T329	1
auto[3]	sw_mode	59	1			T330	1		T331	1		T332	1
auto[4]	boot_req_mode	4	1			T49	1		T333	1		T334	1
auto[4]	sw_mode	83	1			T233	71		T317	1		T252	7
auto[5]	boot_req_mode	3	1			T51	1		T335	1		T336	1
auto[5]	auto_req_mode	6	1			T337	1		T93	1		T338	1
auto[5]	sw_mode	206	1			T57	6		T318	1		T251	2
auto[6]	boot_req_mode	3	1			T339	1		T340	1		T341	1
auto[6]	auto_req_mode	5	1			T319	1		T250	1		T342	1
auto[6]	sw_mode	19	1			T320	1		T343	1		T344	2
auto[7]	boot_req_mode	46	1			T47	1		T88	1		T78	1
auto[7]	auto_req_mode	36	1			T21	1		T22	1		T12	1
auto[7]	sw_mode	998	1			T24	1		T41	1		T43	1