Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	702491	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5810553

1

T1

20

T2

23

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1703483	1			T1	29		T2	27		T3	27
values[0x0]	2222541	1			T1	14		T2	12		T3	14
values[0x1]	2587020	1			T1	10		T2	12		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	342309	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6170735

1

T1

30

T2

29

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25559	1			T6	1346		T26	1		T44	1
valid_sources[0x01]	24444	1			T5	1		T6	1319		T26	1
valid_sources[0x02]	23954	1			T1	1		T6	1333		T73	1
valid_sources[0x03]	25782	1			T6	1403		T73	2		T39	1
valid_sources[0x04]	25823	1			T24	2		T6	1328		T26	1
valid_sources[0x05]	26038	1			T24	2		T6	1244		T64	1
valid_sources[0x06]	25994	1			T1	3		T6	1295		T44	2
valid_sources[0x07]	26437	1			T6	1293		T26	2		T11	1
valid_sources[0x08]	25463	1			T6	1248		T65	1		T41	2
valid_sources[0x09]	24283	1			T24	3		T6	1336		T40	1
valid_sources[0x0a]	26738	1			T24	1		T6	1340		T44	1
valid_sources[0x0b]	26823	1			T6	1235		T36	1153		T8	1
valid_sources[0x0c]	25387	1			T6	1302		T73	1		T39	1
valid_sources[0x0d]	23794	1			T3	6		T6	1258		T73	1
valid_sources[0x0e]	25710	1			T6	1286		T64	1		T39	2
valid_sources[0x0f]	25446	1			T24	2		T4	2		T6	1206
valid_sources[0x10]	24936	1			T2	2		T6	1299		T44	1
valid_sources[0x11]	26729	1			T24	3		T5	1		T6	1392
valid_sources[0x12]	25670	1			T5	1		T6	1394		T65	1
valid_sources[0x13]	25880	1			T3	2		T4	1		T6	1425
valid_sources[0x14]	25087	1			T5	2		T6	1358		T20	1
valid_sources[0x15]	25076	1			T6	1323		T64	1		T44	1
valid_sources[0x16]	28521	1			T6	1272		T44	1		T73	4
valid_sources[0x17]	25528	1			T6	1379		T65	1		T41	2
valid_sources[0x18]	26932	1			T6	1213		T73	2		T41	3
valid_sources[0x19]	25657	1			T24	3		T6	1284		T44	1
valid_sources[0x1a]	25555	1			T3	1		T24	2		T6	1375
valid_sources[0x1b]	25266	1			T24	1		T6	1312		T41	3
valid_sources[0x1c]	25730	1			T6	1362		T44	1		T73	2
valid_sources[0x1d]	25096	1			T1	6		T2	1		T24	7
valid_sources[0x1e]	24112	1			T6	1369		T44	1		T73	1
valid_sources[0x1f]	25738	1			T6	1375		T65	1		T73	1
valid_sources[0x20]	24617	1			T6	1239		T44	1		T45	2
valid_sources[0x21]	25242	1			T2	1		T24	6		T6	1252
valid_sources[0x22]	25150	1			T4	1		T6	1349		T41	1
valid_sources[0x23]	28030	1			T5	1		T6	1299		T41	2
valid_sources[0x24]	24951	1			T5	1		T6	1336		T65	1
valid_sources[0x25]	24871	1			T6	1408		T73	1		T31	3
valid_sources[0x26]	24883	1			T6	1288		T73	2		T41	2
valid_sources[0x27]	25962	1			T6	1320		T65	1		T73	2
valid_sources[0x28]	26119	1			T6	1349		T64	1		T65	1
valid_sources[0x29]	26938	1			T5	1		T6	1344		T73	1
valid_sources[0x2a]	24452	1			T6	1315		T64	1		T65	1
valid_sources[0x2b]	25326	1			T1	2		T5	1		T6	1242
valid_sources[0x2c]	25813	1			T6	1265		T40	1		T17	2
valid_sources[0x2d]	27610	1			T6	1390		T64	1		T65	1
valid_sources[0x2e]	26533	1			T2	1		T6	1353		T73	3
valid_sources[0x2f]	25160	1			T6	1326		T41	1		T20	1
valid_sources[0x30]	25743	1			T6	1328		T44	1		T73	1
valid_sources[0x31]	24796	1			T2	1		T5	1		T6	1370
valid_sources[0x32]	26199	1			T2	1		T24	1		T5	1
valid_sources[0x33]	25530	1			T6	1349		T44	1		T73	2
valid_sources[0x34]	25436	1			T6	1358		T44	1		T41	2
valid_sources[0x35]	27063	1			T2	1		T24	5		T6	1443
valid_sources[0x36]	25747	1			T6	1340		T44	2		T41	2
valid_sources[0x37]	26234	1			T6	1330		T44	5		T73	1
valid_sources[0x38]	26371	1			T6	1383		T44	2		T73	2
valid_sources[0x39]	24494	1			T6	1376		T73	1		T41	1
valid_sources[0x3a]	23995	1			T6	1329		T26	1		T64	1
valid_sources[0x3b]	25132	1			T6	1405		T65	3		T44	1
valid_sources[0x3c]	25289	1			T3	2		T5	1		T6	1364
valid_sources[0x3d]	24822	1			T6	1225		T26	1		T44	2
valid_sources[0x3e]	25624	1			T2	1		T6	1378		T73	1
valid_sources[0x3f]	25773	1			T24	10		T6	1341		T11	2
valid_sources[0x40]	24793	1			T6	1297		T65	1		T44	1
valid_sources[0x41]	25376	1			T5	2		T6	1410		T41	1
valid_sources[0x42]	24674	1			T6	1254		T64	1		T44	1
valid_sources[0x43]	24176	1			T6	1349		T15	1		T55	2
valid_sources[0x44]	24985	1			T2	1		T6	1414		T73	4
valid_sources[0x45]	25953	1			T6	1260		T65	1		T44	2
valid_sources[0x46]	26460	1			T6	1218		T44	1		T41	1
valid_sources[0x47]	25984	1			T1	10		T2	2		T24	1
valid_sources[0x48]	25846	1			T5	1		T6	1397		T44	1
valid_sources[0x49]	24145	1			T1	2		T24	4		T6	1348
valid_sources[0x4a]	25564	1			T6	1367		T41	1		T70	2
valid_sources[0x4b]	25006	1			T24	1		T6	1373		T15	2
valid_sources[0x4c]	26180	1			T6	1400		T41	1		T39	1
valid_sources[0x4d]	24473	1			T6	1403		T46	1		T36	1022
valid_sources[0x4e]	26019	1			T2	1		T5	1		T6	1378
valid_sources[0x4f]	26074	1			T3	2		T5	1		T6	1403
valid_sources[0x50]	25854	1			T6	1359		T64	1		T20	1
valid_sources[0x51]	25197	1			T2	1		T24	2		T6	1307
valid_sources[0x52]	26509	1			T6	1268		T26	1		T41	2
valid_sources[0x53]	24618	1			T1	2		T6	1318		T26	3
valid_sources[0x54]	24726	1			T3	1		T6	1258		T41	3
valid_sources[0x55]	27179	1			T6	1366		T26	3		T73	3
valid_sources[0x56]	25731	1			T2	1		T6	1275		T64	2
valid_sources[0x57]	26295	1			T24	7		T6	1293		T65	1
valid_sources[0x58]	24846	1			T6	1346		T15	1		T40	1
valid_sources[0x59]	25695	1			T6	1351		T64	1		T44	1
valid_sources[0x5a]	24934	1			T6	1270		T26	1		T73	1
valid_sources[0x5b]	25397	1			T6	1420		T44	1		T41	2
valid_sources[0x5c]	24430	1			T1	1		T24	2		T6	1371
valid_sources[0x5d]	25559	1			T6	1337		T44	1		T73	1
valid_sources[0x5e]	24555	1			T2	2		T6	1271		T44	1
valid_sources[0x5f]	24588	1			T24	7		T6	1382		T26	2
valid_sources[0x60]	26520	1			T6	1409		T26	2		T65	1
valid_sources[0x61]	27288	1			T24	1		T6	1295		T65	1
valid_sources[0x62]	25116	1			T6	1307		T44	3		T15	1
valid_sources[0x63]	25850	1			T2	1		T5	1		T6	1393
valid_sources[0x64]	26369	1			T6	1316		T73	3		T41	1
valid_sources[0x65]	24516	1			T6	1327		T41	1		T11	1
valid_sources[0x66]	23224	1			T6	1224		T44	1		T73	2
valid_sources[0x67]	24717	1			T6	1276		T64	1		T44	4
valid_sources[0x68]	26462	1			T6	1331		T73	1		T39	1
valid_sources[0x69]	25580	1			T2	1		T24	3		T6	1254
valid_sources[0x6a]	24734	1			T1	2		T2	1		T24	6
valid_sources[0x6b]	26265	1			T6	1288		T41	1		T40	1
valid_sources[0x6c]	26264	1			T24	4		T5	1		T6	1282
valid_sources[0x6d]	26047	1			T6	1334		T41	2		T70	2
valid_sources[0x6e]	24619	1			T5	1		T6	1246		T32	2
valid_sources[0x6f]	26884	1			T6	1232		T45	2		T20	1
valid_sources[0x70]	25172	1			T6	1322		T26	1		T44	1
valid_sources[0x71]	25144	1			T6	1426		T73	1		T41	1
valid_sources[0x72]	25586	1			T2	2		T6	1291		T73	1
valid_sources[0x73]	24488	1			T6	1279		T64	2		T73	1
valid_sources[0x74]	25770	1			T5	2		T6	1350		T41	1
valid_sources[0x75]	24636	1			T6	1268		T41	3		T15	1
valid_sources[0x76]	25429	1			T6	1292		T73	3		T39	1
valid_sources[0x77]	25539	1			T6	1314		T41	2		T11	1
valid_sources[0x78]	25890	1			T24	2		T6	1284		T73	2
valid_sources[0x79]	26013	1			T6	1297		T44	1		T41	3
valid_sources[0x7a]	25903	1			T6	1259		T44	1		T41	5
valid_sources[0x7b]	24079	1			T6	1185		T40	1		T36	1132
valid_sources[0x7c]	24789	1			T6	1277		T64	1		T44	1
valid_sources[0x7d]	25579	1			T6	1370		T39	1		T11	1
valid_sources[0x7e]	25925	1			T2	2		T6	1258		T44	1
valid_sources[0x7f]	26148	1			T2	1		T3	5		T6	1230
valid_sources[0x80]	26915	1			T6	1309		T65	1		T41	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1460238

1

T1

7

T2

10

T3

13

values[0x0]

all_enables

biggest_size

2177136

1

T1

8

T2

10

T3

10

values[0x1]

all_enables

biggest_size

2173179

1

T1

5

T2

3

T3

3