Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2695	1			T24	3		T10	1		T6	40
non_zero_bins[1]	1891	1			T10	3		T6	33		T44	3
zero	9167	1			T1	7		T2	7		T3	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	500	1			T24	1		T6	12		T41	1
uni	3651	1			T24	1		T10	1		T6	80
gen	4352	1			T1	4		T2	4		T3	3
res	864	1			T10	3		T6	11		T44	1
ins	4386	1			T1	3		T2	3		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8991

1

T1

3

T2

2

T3

2

mubi_true

4762

1

T1

4

T2

5

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

33

1

T56

1

T86

1

T293

1

pass

13720

1

T1

7

T2

7

T3

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	98	1			T24	1		T6	2		T37	3
upd	non_zero_bins[0]	pass	mubi_true	129	1			T6	2		T41	1		T68	1
upd	non_zero_bins[1]	pass	mubi_false	81	1			T6	1		T47	1		T88	1
upd	non_zero_bins[1]	pass	mubi_true	85	1			T6	3		T57	1		T96	1
upd	zero	pass	mubi_false	55	1			T6	3		T36	1		T48	1
upd	zero	pass	mubi_true	52	1			T6	1		T57	1		T98	1
uni	zero	pass	mubi_false	2719	1			T24	1		T10	1		T6	59
uni	zero	pass	mubi_true	932	1			T6	21		T83	1		T46	1
gen	non_zero_bins[0]	pass	mubi_false	502	1			T24	1		T6	6		T74	1
gen	non_zero_bins[0]	pass	mubi_true	536	1			T6	8		T40	1		T46	1
gen	non_zero_bins[1]	pass	mubi_false	327	1			T6	4		T36	1		T88	1
gen	non_zero_bins[1]	pass	mubi_true	352	1			T6	4		T44	1		T43	1
gen	zero	fail	mubi_false	31	1			T56	1		T86	1		T293	1
gen	zero	pass	mubi_false	1861	1			T1	1		T2	2		T3	1
gen	zero	pass	mubi_true	743	1			T1	3		T2	2		T3	2
res	non_zero_bins[0]	pass	mubi_false	192	1			T6	3		T15	3		T40	1
res	non_zero_bins[0]	pass	mubi_true	203	1			T6	2		T39	1		T57	1
res	non_zero_bins[1]	pass	mubi_false	146	1			T6	1		T44	1		T74	1
res	non_zero_bins[1]	pass	mubi_true	143	1			T10	3		T6	4		T73	1
res	zero	fail	mubi_false	2	1			T150	1		T303	1		-	-
res	zero	pass	mubi_false	96	1			T6	1		T11	1		T52	1
res	zero	pass	mubi_true	82	1			T36	1		T37	2		T232	2
ins	non_zero_bins[0]	pass	mubi_false	539	1			T10	1		T6	8		T74	1
ins	non_zero_bins[0]	pass	mubi_true	496	1			T24	1		T6	9		T39	1
ins	non_zero_bins[1]	pass	mubi_false	367	1			T6	7		T15	1		T69	1
ins	non_zero_bins[1]	pass	mubi_true	390	1			T6	9		T44	1		T41	1
ins	zero	pass	mubi_false	1975	1			T1	2		T3	1		T4	2
ins	zero	pass	mubi_true	619	1			T1	1		T2	3		T3	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded